George R. Beatty Email and Phone Number

My name is George Beatty, I am a recent Electrical Engineering graduate with a focus on Digital Design & VLSI from the University of Washington. I'm excited to announce that I'm actively seeking a role in ASIC/FPGA Design. With my strong foundation in both digital and analog design, I'm confident that I can make a valuable contribution to any team.I have experience in RTL Design and back-end flow with cadence and synopsis-based tool flows and a variety of other projects. Most recently, I led a team of three in designing a standard and Out of Order 32-bit RISCV processor for performance comparison. After designing, writing, and simulating RTL in System Verilog, we synthesized the processors with Synopsis DC and verified functionality through simulation in VCS, with results viewed in Verdi Waveform Viewer. Additionally, we generated SRAM blocks for layout using OpenRAM, utilized ICC for APR, and validated our post-APR timing with Primetime. Both designs passed Calibre DRC and LVS checks, and we conducted a PPA analysis to confirm the benefits of the Out of Order processor. Feel free to look at my resume for more details and other projects I've worked on.