Defining future technology development and shaping the product roadmap

Led the implementation and fabrication of two chips funded through DoD programs.1) Low-power, high performance, formally specified cryptographic system with side-channel resistance.2) Low-power, secure machine-vision processor for autonomous applications

After the completion of the Fulcrum Microsystems acquisition from Intel, I stayed with the Datacenter team for another three years and completed a couple of tapeouts and served as the chip timing closure lead for the next product of the group. In 2014 I moved to Intel Labs to further investigate the application of asynchronous circuit technology in forward-looking research projects. Our project was officially announced by Intel in September 2017.

After the Acquisition of TimeLess Design Automation Inc from Fulcrum Microsystems I joined the engineering team there to help with the tapeout of the latest chip. Continued to work on the development of the CAD flow that started as part of TimeLess, but also got involved in physical design and chip development. In September 2011 Fulcrum Microsystems became part of the Intel Corporation Data Center Group.

In April 2008 I co-founded TimeLess Design Automation, which developed a new ASIC flow that enabled designers to automatically generate asynchronous circuits just like ASIC flows that are already available for the synchronous counterparts. The company specialized on CAD tool design and VLSI implementations that apply to the development of asynchronous digital circuits. In August 2010 TimeLess Design Automation was acquired by Fulcrum Microsystems.

Over the span of 8 years I participated in multiple designs for advanced telecommunications' systems with an emphasis on Forward Error Correction encoder/decoder architectures. I lead the hardware implementation of the company's portfolio of Advanced FEC products for PCCC, SCCC and other Turbo-Like codes, such as the company's patented FLDPC codecs. Delivered multiple FPGA designs to customers and lead two ASIC efforts.