Please complete the CAPTCHA to continue
@intel.com
✓
LinkedIn matched
A concise factual answer block for searchers comparing this professional profile.
Gerardo Perfecto is listed as Product Development Engineering Manager at Intel Corporation at Intel Corporation, a company with 10 employees, based in San Francisco Bay Area, United States, United States. AeroLeads shows a work email signal at intel.com and a matched LinkedIn profile for Gerardo Perfecto.
Gerardo Perfecto previously worked as Product Development Engineering Manager at Intel Corporation and Engineering Manager at Intel Corporation. Gerardo Perfecto holds Master'S Degree, Electrical And Electronics Engineering from Iteso Universidad Jesuita De Guadalajara.
This section adds company-level context without repeating Gerardo Perfecto's masked contact details.
AeroLeads found 3 current-domain work email signals for Gerardo Perfecto. Compare company email patterns before reaching out.
17+ years of experience working at INTEL Corporation in Santa Clara. I started working as a Validation Engineer for the DATA CENTERS CPU division group. Leading the Fault Grading SERVER CPU team which evaluated test coverage for high volume manufacturing (HVM) in 3 DATA CENTERS CPU projects. Contributed to develop the new Fault Grading methodologies used for the recent DATA CENTERS CPUs. Worked on the SCAN activities for major DATA CENTERS CPU projects defining ATPG Tools, Flow and Methods (TFM). My latest activities includes Pre-Silicon DATA CENTERS CPU validation, DFx ATPG DATA CENTERS CPU team as a Product Engineer, QUALITY DATA CENTERS CPU MANAGER, PATH-FINDING Burn-In lead and SCAN DATA CENTERS Manager.
Listed skills include Systemverilog, Perl, Vhdl, Testing, and 24 others.
Company context helps verify the profile and gives searchers a useful next step.
A career timeline built from the work history available for this profile.
Santa Clara, California, US
DATA CENTER Manufacturing manager responsible to ensure the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Responsible for the validation and production test for hardware solutions. Tests, validates, modifies and redesigns circuits to guarantee component margin to specification..
Santa Clara, California, US
QUALITY SERVERS CPU manager and SERVERS CPU BURN IN DFX path-finding LEAD (Santa Clara based). Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides.
Santa Clara, California, US
Product Development Engineer in Manufacturing Development Organization Server Division. Relocated from Guadalajara Design Center (GDC) to Santa Clara to support and teach Pre-Silicon ATPG methodologies, flows and tools learned on the TT CoE to the PDE SCAN team. Given the new MDO responsibilities. Responsible for ensuring the testability and.
Santa Clara, California, US
Hardware Engineer responsible for Fault-Grading (FG) activities on Intel’s Server Microprocessors. Responsibilities include: team leader and FG planning, development and execution. Contributor to Architecture Validation (AV) and responsible for AV test database (AVTB) activities which include tool maintenance and users support. Responsible for ATPG.
Santa Clara, California, US
Validation engineer responsible for the Intel Architecture Validation (IAV) and Feature Architecture Validation (FAV) activities as well AV test database (AVTB) activity owner. Responsible for the Intel Architecture validation (legacy) and Feature Architecture Validation (Full chip validation) on Servers which includes test content development and.
Other employees you can reach at intel.com. View company contacts for 10 employees →
Zemach Green
Colleague at Intel Corporation
Israel, Israel
View →
CM
Colleen Martinez
Colleague at Intel Corporation
Greater Phoenix Area, United States
View →
AH
Agus Hendro
Colleague at Intel Corporation
Chandler, Arizona, United States, United States
View →
AK
Anna Kambhatla
Colleague at Intel Corporation
Portland, Oregon, United States, United States
View →
WW
Wei Wei
Colleague at Intel Corporation
Hillsboro, Oregon, United States, United States
View →
VD
Vraj Dalwadi
Colleague at Intel Corporation
Ahmedabad, Gujarat, India, India
View →
MH
Mei Har W.
Colleague at Intel Corporation
Bayan Lepas, Penang, Malaysia, Malaysia
View →
LS
Laura Spinella
Colleague at Intel Corporation
Pisa, Tuscany, Italy, Italy
View →
DO
Devyn Ooi
Colleague at Intel Corporation
Bayan Lepas, Penang, Malaysia, Malaysia
View →
JL
Jinhai Li
Colleague at Intel Corporation
Rio Rancho, New Mexico, United States, United States
View →
Quick answers generated from the profile data available on this page.
Gerardo Perfecto works for Intel Corporation.
Gerardo Perfecto is listed as Product Development Engineering Manager at Intel Corporation at Intel Corporation.
AeroLeads has found 3 work email signals at @intel.com for Gerardo Perfecto at Intel Corporation.
Gerardo Perfecto is based in San Francisco Bay Area, United States, United States while working with Intel Corporation.
Gerardo Perfecto has worked for Intel Corporation.
Gerardo Perfecto's colleagues at Intel Corporation include Zemach Green, Colleen Martinez, Agus Hendro, Anna Kambhatla, and Wei Wei.
You can use AeroLeads to view verified contact signals for Gerardo Perfecto at Intel Corporation, including work email, phone, and LinkedIn data when available.
Gerardo Perfecto holds Master'S Degree, Electrical And Electronics Engineering from Iteso Universidad Jesuita De Guadalajara.
Gerardo Perfecto is listed with skills including Systemverilog, Perl, Vhdl, Testing, System Verification, Linux, Verilog, and Atpg.
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trial Search contacts