Gerardo Perfecto Email & Phone Number

Santa Clara, California, Us

DATA CENTER Manufacturing manager responsible to ensure the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Responsible for the validation and production test for hardware solutions. Tests, validates, modifies and redesigns circuits to guarantee component margin to specification. Analyzes and evaluates component specification versus performance to ensure optimal match of component requirements with production equipment capability with specific emphasis on yield analysis and bin split capability. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and appliesconcepts for optimizing component production relative to both quality and cost constraints. Autonomously plans and schedules own daily tasks, develops solutions to problems utilizing formal education and judgment

Santa Clara, California, Us

QUALITY SERVERS CPU manager and SERVERS CPU BURN IN DFX path-finding LEAD (Santa Clara based). Plans, provides resources for and directs activities in engineering function to meet schedules, standards, and cost. Cultivates and reinforces appropriate group values, norms and behaviors. Identifies and analyzes problems, plans, tasks, and solutions. Provides guidance on employee development, performance, and productivity issues. Plans and schedules daily tasks, uses judgment on a variety of problems requiring deviation from standard practices. Inadequacies and erroneous decisions would cause moderate inconvenience and expense.

Santa Clara, California, Us

Product Development Engineer in Manufacturing Development Organization Server Division. Relocated from Guadalajara Design Center (GDC) to Santa Clara to support and teach Pre-Silicon ATPG methodologies, flows and tools learned on the TT CoE to the PDE SCAN team. Given the new MDO responsibilities. Responsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp. Contributions in design, development and validation of testability circuits. Evaluation, development and debug of complex test methods. Analyzes early customer returns with emphasis on driving test hole closure activities. Creates and applies concepts for optimizing component production relative to both quality and cost constraints. Autonomously plans and schedules own daily tasks, develops solutions to problems utilizing formal education and judgment.

Santa Clara, California, Us

Hardware Engineer responsible for Fault-Grading (FG) activities on Intel’s Server Microprocessors. Responsibilities include: team leader and FG planning, development and execution. Contributor to Architecture Validation (AV) and responsible for AV test database (AVTB) activities which include tool maintenance and users support. Responsible for ATPG development and execution activities on Intel’s Server Microprocessors including team leadership, planning, development and execution.Fault grading/ATPG:- Unix/Linux environment.- RTL system validation.- Gate level system debug.- VHDL - System Verilog.- Scripting - PERL.- HVM testing.- TAP.- ATPG.- SCAN.

Santa Clara, California, Us

Validation engineer responsible for the Intel Architecture Validation (IAV) and Feature Architecture Validation (FAV) activities as well AV test database (AVTB) activity owner. Responsible for the Intel Architecture validation (legacy) and Feature Architecture Validation (Full chip validation) on Servers which includes test content development and execution; as well responsible for the Architecture Validation Test Base, which includes environment development/maintenance and clients support.

Master'S Degree, Electrical And Electronics Engineering

Post-Graduate Diploma, Integrated Circuit Design

Bachelor Of Engineering (B.E.), Electrical And Electronics Engineering