Entrepreneur at my newly-formed company Unific, focusing at top-level IC design, with 20 years of background in analog and mixed-signal design.Interested? Please send me an e-mail at info@unific.nl.My brand new website has gone live! Check out all my activities @ Unific here:unific.nl

76-81GHz Car Radar Integrated Transceiver IC in 40nm CMOS technology - integration lead, responsible for pinning definition, power plan, top-level schematic, floor-planning, top-level layout, physical verification and IO ring / ESD design- co-design of embedded wafer level ball grid array (eWLB) package with the IC, definition of PCB bump assignment, realisation of Re-Distribution Layer (RDL) design which connects the bumps to the IC using only one interconnect layer, while safeguarding interference isolation- main interface to the digital IP team for efficient communication and delivery of digital IP blocks- set-up and configuration of the DesignSync server, database managerDigital Audio Broadcasting (DAB) receiver supporting VHF-3 & L-Band in 65nm CMOS technology- integration lead, responsible for top-level schematic and layout, physical verification, chip-finishing and final sign-off, with a special focus on interference isolation issues- part of the technical core team- transfer to business line, off-loaded tasks (ESD design) from radio front-end integator- schematic review, floor-planning and layout parts in wideband ADC sub-IP60GHz receiver front-end for beam steering communication applications in 45nm CMOS technology- top-level integrator and ESD designDesign of an 11-bit 3.6GS/s time-interleaved SAR Analog-to-Digital Converter in a 65nm CMOS process- top-level integrator, responsible for top-level schematic and layout of the SAR ADC, its ESD design and complex layout of some high-performance sub-blocksDesign, layout and measurement of Radio-Frequency (RF) circuits in CMOS technologies for multi-band Ultra Wide Band systems, with applications in the field of wireless USB: a multi-site System-on-a-Chip integration project of a complete Ultra Wide Band PHY (physical layer)- integration lead of the radio front-end of this PHY, and interface person to the digital base-band and MAC teams

Design, layout and measurement of Radio-Frequency (RF) circuits (in a SiGe process) for multi-band Ultra Wide Band systems, aiming at large data-rate wireless communication at short distances. Challenges are the large signal band (528MHz wide channels), the high local oscillator (LO) frequencies (3-5GHz) with good spectral purity, fast hopping between channels, low noise figure and immunity to large interferer systems. This was a multi-site project, in close cooperation with several Philips groups.Design, layout and measurement of CMOS circuits with a high timing accuracy (crystal oscillator, PLL with LC oscillator, digital counter) for application in low-rate (1Mb/s) Ultra Wide Band systems based on pulse positioning of ultra-narrow pulses.Design, layout and measurement of high-speed CMOS sigma-delta ADC's, aiming to find out themaximum usable sampling frequency (up to 1GHz). Challenges are sampling clock jitter, waveform asymmetry of feedback DAC pulses, and minimizing loop time delays.Design, layout and measurement of a high-speed (co)-processor in a sector-wide project (sector IC Design of Philips Research Eindhoven). Goal was to find the optimal way of designing digital circuits running well above 2GHz, both using standard cell libraries and custom made digital cells.Design, layout and measurement of a switched-capacitor channel filter for teletext applications. Thefilter enhanced the signal frequency band around 1.5MHz and compensated for channel loss.Design, layout and measurement of a teletext front-end, consisting of a differential variable gain amplifier and a differential 7-bit two-step Analog-to-Digital Converter. Main challenges were power and area reduction, and the fully differential approach.