Gary Hunter Email & Phone Number

Ireland

Ireland

Member of staff for Intel’s Neural Processing Unit (NPU) IP organisation. My key contribution are:• Drive IP product feature definition in partnership with Intel’s Client Product Architecture groups, Customer Engineering groups, Business and Marketing teams and NPU Hardware and SW architecture teams.• Owner of IP Plan of Record feature definition intercepting Intel’s Client product roadmap.• Point of Contact for Intel wide AI execution forums representing the NPU IP organisation.• Weekly report of NPU IP Organisation execution to Intel’s Senior VP of Graphics and AI execution.• Lead teams of senior engineers to drive all aspects of execution across IP Hardware and Software.

Ireland

Following Intel’s acquisition of Movidius in 2017, merged into Intel’s AI Vision SoC team. My key contribution were:• Design lead for High-Speed Interfaces on next gen AI Vision Soc for Digital surveillance camera market.• Drove IP vendor selection for Analog PHY and Digital controllers for DDR, PCIe and USB protocols.• Lead design team execution for RTL, validation and sign-off for High-speed IO resulting in zero post-si findings on the interfaces.• Assumed ownership of Production engineering for Movidius existing portfolio of Myriad products to ensure they met Intel’s product quality standards. Lead a team of test program engineers and quality and reliability experts to increase yields, tighten parametric test to increase quality and to reduce test time and product cost.

Member of the senior leadership team reporting to the VP & GM of the IoT and Wearables Group. My key contribution were:• Built a front-end engineering team from 3 to 50 people covering RTL Design, FPGA Emulation and Post-Si verification.• Responsible for the Low-speed peripheral and Power Management Architecture of Intel’s 1st IoT SoC (Quark™)• Lead design execution of IoT and Wearable SoC development resulting in three 1st stepping production silicon products.• Lead Post-Si execution on IoT and wearable products including Functional and Electrical validation and qualification. Reduced overall execution time from Intel standard 12 month to 6 months through execution innovation and statistical data analysis.• Won the Intel Achievement award in 2014 for me contribution to launching the Quark™ product line.

Senior II Hardware design engineer working on Synopsys’ range of Digital IP Cores, my key contributions were:• Lead designer of the PCI Express to AMBA 2 (AHB) and AMBA 3 (AXI) bridge module which forms an optional part of the PCI Express IP Core.• Completed all RTL changes as part of a complete VMM based re-verification of the bridge products.• Architected, implemented and drove verification of seven PCI-SIG Engineering Change Notifications (ECN’s).• Leader of a release team responsible for delivery of several early adopter (EA) and general availability (GA) releases of the PCI Express IP Core.• Provided direct customer support to several large customers including system debug and IP enhancement requests.• Enhanced the AMBA 2 (AHB) DMA controlled to support defined length bursts as well as undefined length bursts.

FTDI are specialists in converting legacy peripherals to USB (Universal Serial Bus). Based in Glasgow as a Senior Design Engineer my key contributions were:• Reviewed and re-wrote legacy code to improve RTL coding style.• Took ownership of in-house synthesis and the management of place and route activity through a 3rd party design company.• Successfully taped out early test chip into TSMC test wafer.• Provided mentoring and supervision for other hardware engineering staff.

Senior Development Engineer and Project Manager, my key contributions were:• Engineering Lead for the silicon backplane design of a Polymer OLED micro-display.• Managed team of two in house digital designers and 3rd party analogue design team.• Managed design and delivery of demonstration modules used for marketing of the micro-display product.

A Senior Digital Design Engineer my key contributions were:• Designed digital core of an S/PDIF transceiver chip.• Designed various sub-modules including I2S, I2C and audio limiters for use in audio codec IC’s.• Responsible for Synthesis and Place and Route of several Mixed Signal IC tape outs.• Developed a floorplan methodology that worked closely with Wolfson’s in house analogue layout tools to automate the generation of digital floorplans used by the place and route tools.

As a graduate, my key contributions were:• Design, schematic capture and layout supervision of functional blocks operating at 2.5 Gbit/s data rates

Masters Of Engineering, Electronics

Final Year Subjects Digital Communications, Systems Theory, Radio Frequency Engineering, Microelectronic Circuits, Circuit Theory and VLSI.

Cpdc In Management And Leadership

Education record