• Program Managemento Drove the production of DC to AC power inverters for the Trident II D5 Ballistic Missile System through expert management of resources, schedules, and costs.o Established and managed a dynamic Inventory System, optimizing resource utilization and enhancing production efficiency.o Conducted proactive monthly Risk meetings with customers, mitigating potential issues and ensuring project alignment.o Delivered weekly updates to customers and the CEO, fostering transparent communication and client satisfaction.o Orchestrated weekly Quality Assurance team meetings, ensuring strict compliance with AS9100D standards.o Spearheaded Configuration Control Management for meticulous documentation and version control.• Technical Leado Led the engineering team in developing and updating Verification and Acceptance Test plans for Trident II D5 Ballistic Missile System’s Missile Inverter (MINV) and Destruct Inverter (DINV).o Oversaw comprehensive testing phases, including Board Level, System Level, Environmental, and Shock and Vibe testing.o Collaborated with customers and DCMA during Acceptance testing, ensuring successful project milestones.o Conducted monthly deficiency meetings with engineering and production teams, identifying root causes and implementing corrective actions.

• Hardware Design and Testing:o Led software development efforts to test embedded processor serial interfaces (Ethernet, RS485, RS422, MIL-STD-1553, ARINC-429o Managed resources and tasks to execute required testing procedures for the AN/UPX-123A Common Transponder, UPX-41C Digital Integrator, and AN/UPX-29 System• FPGA/CPLD Design and Integration Metrics:o Led the FPGA Configuration Control Board and facilitated FPGA design reviews.o Coordinated system-level certification testing for the AN/UPX-29 System.o Coordinated bench level testing of FPGAs integration on VME digital circuit cards.• Technical Leadership and Collaboration:o Acted as the Mode S Project Lead, managing project schedules, budgets, and spending plans to provide Mode S capability to AN/UPX-29 Systems.o Conducted monthly Project Team Meetings and Risk Management Meetings, resulting in a 90% reduction in project risks identified and mitigated, ensuring adherence to cost, schedule, and technical performance requirements.• Documentation and Compliance Metrics:o Developed the Systems Engineering Master Plan (SEMP) and Engineering Change Proposal for the Mode 4/5 Cryptographic Computer, ensuring compliance with regulatory requirements and approval from relevant stakeholders.o Represented the US Navy at national technical working groups and conferences to develop Mode 5 standards and produce key documentation, including the Standard NATO Agreement for Mode 5 IFF.

• Design of Encrypted CompactFlash Cardo Engineered the design of an encrypted CompactFlash card, leveraging the Hitachi AND flash chipset and controller in conjunction with a Xilinx Virtex II FPGA.o Implemented robust encryption measures by integrating a Triple DES IP core, operating at 200 MHz.• Development of VHDL Codes for Wiegand Decodero Developed VHDL codes for a modified Wiegand decoder on a SpartanXL CPLDo Contributed to the enhanced functionality of the HID Prox card reader for secure military applications.

• Led the end-to-end design of a processor-based circuit board featuring a CompactPCI form factor, incorporating components such as a 66 MHz bus, SDRAM, Flash memory, Hot Swap capability, and Programmable Logic Devices (PLDs).• Designed glue logic for the integration of a PowerPC (Motorola 860) processor and PCI Bridge.• Implemented external SDRAM refresh cycles in an Altera CPLD, addressing and correcting bus errors.

• Development of Test Procedures for 10G OC-48 Regenerator• Technical Liaison and Outsourcing Oversight for the OC-48 TDM Mux• Audit of Sentry Power Supply Manufacturing Process• Technical Support for Metro OC-3/12 Transceivers

• Led the circuit board design for the Radar Receiver Jammer Interface Controller (RJIC), a critical component operating at a frequency of 50 MHz and utilizing the VME (Versa Module Europa) standard as a peripheral interface.• Ensured the design met stringent requirements for compatibility, reliability, and performance within the radar jamming system.• Orchestrated the design of four Xilinx FPGAs utilizing VHDL, demonstrating proficiency in hardware description language and FPGA programming.• Implemented glue logic, an SDRAM controller, VME interface for seamless integration, and functionality to queue radar jamming sequences.• Developed a robust system to report executed jams and missed jams, enhancing the intelligence and effectiveness of the radar jamming capabilities.• Designed digital circuits including data buffering mechanisms using First-In-First-Out (FIFO) structures, ensuring efficient and reliable handling of data within the RJIC system.• Played a pivotal role in the selection of components, including VME chipsets and FPGAs, demonstrating a keen understanding of system requirements, compatibility, and performance criteria.• Ensured seamless integration of selected components into the RJIC, optimizing the overall functionality and reliability of the radar jamming interface.

• Technical Support for Programmable Logic Devices at Arrow Electronicso Served as a key technical support resource at Arrow Electronics, specializing in a diverse range of programmable logic devices (PLDs) and their associated development tools.o Provided expertise and guidance for Altera's Complex Programmable Logic Devices (CPLD) and Field-Programmable Gate Arrays (FPGA), Vantis CPLD and FPGAs, as well as Lucent's ORCA CPLDs.• Customer Support and Issue Resolutiono Addressed and resolved technical inquiries from customers related to the functionality, programming, and integration of programmable logic devices.o Assisted clients on-site in troubleshooting issues, providing clear and concise guidance to ensure the successful implementation of programmable logic solutions.• Product Knowledge Disseminationo Conducted training sessions and workshops to disseminate in-depth knowledge about Altera's CPLD and FPGA, Vantis CPLD and FPGAs, Lucent's ORCA CPLDs, and other programmable logic devices.o Shared insights into the practical application of development tools associated with these devices, empowering clients with the skills needed for effective utilization.• Stayed Abreast of Technological Advancementso Kept abreast of the latest advancements in programmable logic technologies, ensuring a proactive approach in advising clients on the most current and suitable solutions for their projects.o Collaborated with manufacturers and engineers to stay informed about product updates, emerging trends, and industry best practices.

• Joined the Electronics Systems Division/Identification System Department in the capacity of an Electrical Engineer I, contributing to cutting-edge projects in electronic systems development.• Provided crucial digital design support for the Mode 5 project, demonstrating a strong grasp of digital electronics principles and applications.• Led the design and development of a Common Logic Card featuring a VME bus interface, showcasing expertise in designing for compatibility and standardized communication protocols.• Designed and implemented highly specialized transponder waveform generators and interrogation waveform generators, contributing to the critical functionality of the Mode 5 system.• Played a key role in providing digital support for the design of the Mode 5 correlator, contributing to the development of a sophisticated system for signal processing and correlation.• Created a comprehensive memory map, outlining data storage and retrieval strategies crucial for efficient system operation.• Designed glue logic in FPGA, incorporating address decoders, ready generation circuits, interrupt encoders, and control signals for SRAMs, along with various interfaces.• Utilized industry-standard tools including OrCAD Schematic, VHDL, Aldec, Xilinx Foundation (including simulator), and XACT for FPGA design, ensuring adherence to best practices in electronic design automation.• Edited Configurable Logic Blocks (CLBs) and leveraged the LCA editor (XACT) to fine-tune and optimize FPGA configurations.