Gilles Dondorp Email & Phone Number

Nieuwegein, Ut, Nl

Gouda

Responsible for the program management of projects for Science&Industry. These projects comprise system engineering, the realization of custom electronics, firmware, programmable logic, mechanics, etc. and the integration of these technical solutions within the customer's system. Activities: overall planning of projects, resource management, setting up development teams, project acquisition and greenfield market exploration.

Gouda

Enschede

Recore Systems develops and designs heterogeneous many-core processor systems with the mission to make the many-core life easy. The system includes HW subsystems and many-core software managing the runtime mapping of the application on the HW. Key properties are; embedded, reliable and power efficient.

Responsible for the verification of the WiFi IC developed by the Broadcom team in Bunnik.

LTE Project:- As a Technical lead I managed & coached 4 designers and verification engineers - Set up a verification team (3 engineers) including the recruitment of new talents- Renewed the verification process by changing over to new hardware verification techniques (OVM / SVL) and a new tool set (Cadence)- Managed the planning and deliverables of the verification team and ASIC team.- Worked on a renewed issue management process for both internal and external users.- Cooperated with multiple engineering teams located in the Netherlands, France and the US

WiMAX ASIC Project:- As a Technical lead I managed & coached 4 designers of the MAC sub system team- Project manager on the Motorola side of the project that counted 14 internal engineers, 3 consultants and a foundry team (+/- 15 engineers).- Managed the foundry selection process including the Request for Information (RFI) and Request for Quotes (RFQ), Statement of Work (SOW) and quality documents like the procurement specification (51R).- Managed the communication, project deliverables and issues with the Foundry and the internal HW and SW teams.- Since we finished the first ASIC (June 2007) I managed the interface with the customer support team on all ASIC-related issues.- Outsourcing verification work and recruiting consultants- Defined the functional specification of pinout and all required muxing and control.- Written the MAC Subsystem Requirements specification composed in close cooperation with the SW team- Implementation of the Change Request Process and the related bug tracking process using Clearquest

- Managing the WMAC project team of 8 designers / verification engineers located in Nieuwegein and Allentown (US)- Delivered a cost reduced version of the Wi-Fi MAC controller Hermes 2.5 where we made a technology step (.2 micron) and added AES and a PCI Master interface.- Delivered a power (and cost) reduced version of the Wi-Fi MAC controller Hermes 3 where we made a technology step (.13 micron) and added USB 2.0 OTG.- Introduced a new high level verification language (Specman) for the verification of the IC.

The Wireless Communications and Networking Division (WCND) of Lucent Technologies is noted to be the inventers of Wi-Fi.- Worked on multiple Wi-Fi mixed signal IC's (Ariadne, Deadalus and Theseus). Building the transmitter, the serial modem data interface, the power control interface and the test interface.- Worked on the Wi-Fi Medium Access Controller IC (Hermes). Building the WEP engine, Memory controller, SPI interface.- Responsible for the toplevel verification of the MAC. developed an automated verification environment using AWK and UNIX scripts.- Build a power model (Excel) to estimate the power numbers for the MAC which matched closely with the final numbers.

- Modem emulator (Xilinx FPGA, 7K gates):The Hermes team required a tool which emulated the interface to the DSP including the phy, to develop the initial 802.11 FW. We developed a dedicated FPGA platform to enable this where I was responsible for the FPGA design en testing of the platform. - Test-pattern-generator (Xilinx FPGA, 4K gates): This FPGA was generating several test patterns that were required for the functional test system to test the products.- Ariadne ASIC (standard cell ASIC in 0.5 micron CMOS, 10K gates): The schematics had to be ported from an existing FPGA design to the ASIC library, the functionality had to be extended and the power management was improved with gated clock structures.

Bachelor Of Science

Intermediate Technical College