Design Verification Engineer
CurrentDevelop and execute test plans to ensure high-quality RTL verification and early detection of critical design issues. Collaborate with design and architecture teams to define verification requirements and create comprehensive test plans. Utilize advanced verification environments with UVM, SVA, SystemVerilog Coverage to enhance design coverage and verification efficiency. Conducted in-depth performance analysis of cache Quality of Service (QoS) techniques in multi-core processor systems and performed fault injection tests to assess the resilience of safety-critical systems. Additionally, mentored and trained junior engineers to foster their professional growth within the organization.