Giovanni Meciani Email & Phone Number

Oslo, Norway

• IP Verification (QuestaSim)
• Created from scratch UVM testbench for I2C. Used 3rd party VIP for protocol verification.
• Created and executed C-tests for RRAM controller, used at product level to verify IP's spec.
• Created process to synthesize IP for co-simulation with Cadence Emulator.ASIC prototyping (Vivado, Precision Synthesis, Xcelium)
• FPGA - ProFPGA with AMD Xilinx Ultrascale+. Produced FPGA images from synthesis to place and route, devised appropriate clocking scheme, adapted timing and physical constraints, designed synthesizable models.
• Emulator - Cadence Palladium Z1. Product database delivery and support, as well as firmware tests execution using J-Link.Digital design

Almelo, The Netherlands

Development of a synthesizable processing algorithm, DSP domain. Target product was Industrial ScopeMeter FLUKE 125B. Project embedded in the Master Degree programme.Xilinx, Artyx 7, VHDL.

Saarbrücken Area, Germany

Development of a prototypical FPGA-based microarchitecture (based on ARMv4) that was specifically designed for use in time-critical embedded systems. Part of the Erasmus Exchange programme.Verilog/SystemVerilog. Terasic DE2-115.

Embedded Systems, Electrical And Electronics Engineering

Implementation of a BFSK demodulator written in VHDL and synthesized for Intel FPGA. Used VUnit to parallelise verification. Also.

Bachelor Computer Engineering, Electrical And Electronics Engineering / Computer Science