Giuseppe Giuffrida Email and Phone Number

Develop component schedules and lead their execution to support MTX roadmap, including oversight of organization headcount, operating expense budgets, and capital budgets.

Lead the team responsible for definition, implementation and optimization of wafer level test methodologies and conditions throughout the life cycle of 3DXP Memory products. Responsibilities include development and validation of new test modes to optimize yields, wafer level and unit level testing and manufacturing efficiency, testing time, quality and reliability of the products.

Lead the team responsible for design, implementation, validation and execution of measurement tests to assess eMMC performances at system level (e.g. mobile platforms such as Panda Board). Responsibilities include preparation of the laboratory (HW/SW definition and identification of suitable testing equipment), test cases design against either Jedec specifications or customer usage models, delivery of accurate and concise validation reports to internal customers.

Responsible for managing technical projects to align product performance and manufacturing flows across Wireless Business Unit products. Provide technical leadership and direction for the department by defining and prioritizing projects, identifying and analyzing issues and risk, and allocating resources to meet timelines and deliverables. Represent the business unit on cross-functional teams and work with Manufacturing, Planning and other operational and development groups to provide training and consultation on capacity planning and product capability. One of the main activity consisted of supporting 45nm technology node transfer from 200mm wafer fab (Israel) to 300mm wafer fab (US).

Lead the Sort Team responsible for the product/process validation of the first NOR Flash Memory produced using 45nm technology node. The team had a key role in supporting the definition of engineering trials to ensure reliability and provide technical feedback about product/process health to Design Engineering, Process Engineering and Quality teams. The team developed the code to enable product validation at wafer level, manufacturing startup and high-volume ramp up (Israel).

Responsible for monitoring test results to identify opportunities for improvement and to recommend quality checks. Collaborate with the design team to define test flows aligned to available hardware resources and ensure coverage. Other responsibilities include engagement in productivity and yield improvement activities, provide training on internal mode specifications and participate in continual improvement initiatives.

Responsible for the development of test programs for wafer level testing on different ATEs (Advantest, Agilent, Credence, Teradyne and Versatest). Other responsibilities include design validation, product validation and technical support in the form of documentation, training and failure analysis during product qualification and manufacturing startup (Singapore and Catania).