Giyoung Yang Email & Phone Number

San Diego, CA, US

San Diego, California, United States

Design Analysis and Debug for Intel Product enabled on External Foundry Manufacturing - Development of methodology to find the root cause of HVM production yield loss by utilizing EDA tools- eProfiling framework (STA + Spice simulation) development based on the Volume-Diagnosis Callout- pProfiling framework (Layout Pattern Analysis) development based on.

Hwaseong, Gyeonggi, South Korea

• Development high-density and low-power standard cell library and customer support for 3nm GAA process. - Multi-bit flip-flop cell library development for low-power application for general foundry customers - High-sigma.
• Development high-density and low-power standard cell library based on 4nm FinFET process. - New standard cell design that improves sub-SoC block area by combining different function cells - Low-power flop-flop circuit.

Hwaseong, Gyeonggi, South Korea

• Design Technology Co-Optimization (DTCO) work for 4nm FinFET and 3nm GAA process - Analyze and interpret PPA for cell-level DTCO with sub-SoC block-level timing analysis - Parasitic RC and device model analysis and.

Hwaseong, Gyeonggi, South Korea

• Development standard cell architecture and evaluation for 10nm/8nm FinFET process - Standard cell architecture design for high performance application - Analyze and interpret Power, Performance, and Area (PPA).

Hwaseong, Gyeonggi, South Korea

• Development SRAM macro architecture and implement SRAM yield-vehicle for 14nm/10nm FinFET process - Transistor-level SRAM read/write assist circuit design for enhancing SRAM bitcell stability - Silicon failure data.