• Professional Skill set- Standard Cell Library and SRAM Test-Vehicle Development : PDK/ DRC/ LVS/ StarRCXT/ QRC/ Hspice/ Finesim/ Virtuoso/ Solido HSV- Physical Design for Library Verification : Primetime/ IC Compiler/ Design Compiler- Product Engineering for Yield Enhancement : Yield Explorer/ Avalon/ JMP/ Primetime/ Hspice/ LVS/ DRC/ QRC/ Pegasus CPA/ Calibre Pattern Matching - Scripts Language : Cshell/ JSL/ Python• Career History- [2022.10-Current] Senior Engineer, Manufacture Quality Enhancement Team, Intel Product, Intel Corporation- [2019.03-2022.09] Staff Engineer, Design Enablement Team, Foundry Business, Samsung Electronics- [2017.03-2019.02] Master degree, Electronics and Computer Engineering, Seoul National University
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Staff EngineerIntel CorporationSan Diego, Ca, Us -
Senior EngineerIntel Corporation Oct 2022 - PresentSan Diego, California, United StatesDesign Analysis and Debug for Intel Product enabled on External Foundry Manufacturing - Development of methodology to find the root cause of HVM production yield loss by utilizing EDA tools- eProfiling framework (STA + Spice simulation) development based on the Volume-Diagnosis Callout- pProfiling framework (Layout Pattern Analysis) development based on the Volume-Diagnosis callout
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Staff EngineerSamsung Semiconductor Mar 2021 - Sep 2022Hwaseong, Gyeonggi, South Korea• Development high-density and low-power standard cell library and customer support for 3nm GAA process. - Multi-bit flip-flop cell library development for low-power application for general foundry customers - High-sigma analysis for verifying standard cell reliability for mobile applications• Development high-density and low-power standard cell library based on 4nm FinFET process. - New standard cell design that improves sub-SoC block area by combining different function cells - Low-power flop-flop circuit and layout design by reducing redundant clock power consumption -
Staff EngineerSamsung Semiconductor Mar 2019 - Feb 2021Hwaseong, Gyeonggi, South Korea• Design Technology Co-Optimization (DTCO) work for 4nm FinFET and 3nm GAA process - Analyze and interpret PPA for cell-level DTCO with sub-SoC block-level timing analysis - Parasitic RC and device model analysis and finding design knobs based on path-finding PDK - Optimizing standard cell circuit and layout design for PPA benefits based on process definition
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EngineerSamsung Semiconductor Mar 2015 - Feb 2017Hwaseong, Gyeonggi, South Korea• Development standard cell architecture and evaluation for 10nm/8nm FinFET process - Standard cell architecture design for high performance application - Analyze and interpret Power, Performance, and Area (PPA) projections for cell-level DTCO
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Assistant EngineerSamsung Semiconductor Jul 2011 - Feb 2015Hwaseong, Gyeonggi, South Korea• Development SRAM macro architecture and implement SRAM yield-vehicle for 14nm/10nm FinFET process - Transistor-level SRAM read/write assist circuit design for enhancing SRAM bitcell stability - Silicon failure data analysis and modeling device and wire models for SRAM macro
Giyoung Yang Education Details
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Electrical And Computer Engineering
Frequently Asked Questions about Giyoung Yang
What company does Giyoung Yang work for?
Giyoung Yang works for Intel Corporation
What is Giyoung Yang's role at the current company?
Giyoung Yang's current role is Staff Engineer.
What schools did Giyoung Yang attend?
Giyoung Yang attended 서울대학교 (Seoul National University).
Who are Giyoung Yang's colleagues?
Giyoung Yang's colleagues are Khayadada Sreedhara, Esteban Badilla Barrantes, Carina Hahn, Liam Frost, Luciane Apolinario, Greg Hunt, Kishore K.t..
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