Gopalakrishnan Krishnan Email & Phone Number

Bengaluru, Ka, In

Bangalore Urban, Karnataka, India

Lead ADI's Digital IP team, focusing on - High Speed Interfaces & Protocols - Processor Cores + Collaterals (general purpose, DSP, NN cores) - Standard Peripherals

Bengaluru, Karnataka, India

Handled a diverse range of technical, engineering, and operational responsbilities at EdgeQ.- SoC Architecture & Sub-systems micro-architecture (DDR sub-system, IO sub-system, eCPRI s/s, high speed NoCs, interrupts, secure boot infrastructure)- Performance analysis & KPIs for product use-cases- IP evaluation, procurement & liaison (high speed Serdes, MSIPs, multiple digital IPs)- Lateral hiring & mentoring across multiple functions (DE, DV, DFT, Emulation)- Silicon bring up lead- ATE & Qual Strategy

Bengaluru Area, India

Developed multiple successful prototypes (invasive and non-invasive ultrasonic) of IoT enabled smart water meters. Developed the software infrastructure to measure water consumption, and deployed the complete solution successfully to customers.

Ramped up the semiconductor services business from scratch to a revenue of 1M$ in less than 1.5 years. Groomed and led a team of 40 engineers on technical and business aspects.Bootstrapped the business to profitability by offering differentiated semiconductor services in digital design, and turnkey product development.

Bengaluru Area, India

Contributed to architecture definition of Snapdragon 660 and 630 high tier SoCs.Worked on Qualcomm Snapdragon Processors, focusing on the architecture & SoC level specifications. • Deep involvement in architecture/micro-architecture for next generation smartphone System-On-Chips (SoCs)• Strong understanding of smartphone features/use-cases and their data flows, bandwidth requirements, power envelopes- thereby contributing to Power/Performance/Area (PPA) optimization analysis and tradeoffs• Extensive interaction with Cross Functional Teams such as Product Management, Chipset Architecture, SoC Engineering, SW Leads, Worldwide IP Core teams, Product/Test Engineering etc. - analyzing PPA tradeoffs, HW/ SW interfaces and re-usability of various IPs/ Cores• Driving Die Area Analysis & refinement, and bottoms-up/top-down What-If Analysis for product conceptualization- In-depth knowledge of various sub-systems/Interfaces/SoC Infrastructure such as Processor, DDR, on-chip interconnect, Multi-Media sub-systems like Camera, Display, Video engine, Audio, Sensor, Compute Vision and GPU• Use-case driven Clocking Analysis and impact to power across different use-cases. Strong understanding of Power/Performance use-case dashboard, DCVS (Dynamic Clock Voltage Scaling) techniques and Low Power Methodologies in 14nm/10nm geometries, and their implications to Power & Performance

Bangalore

Chip Lead for Metro Ethernet Switch Chips on 28nm technologya. Co-Chip Lead for first 28nm Ethernet Switch SoC from India Centerb. Tracked schedule, milestones, and deliverables from CFTs across India, UK, and US centersc. Coordinated Design Engineering (DE), Design Verification (DV), Emulation, Physical Design, and DFT efforts at India centerd. Active contribution to low power architecture, package finalization, System Validation Kit developmente. Drove reviews for IP integration, STA, Physical Design, and DFTf. Drove PTPX based power estimation efforts

Bangalore

• Developed multiple image signal processing chips and SoCs• Worked on Image Co-Processor (ICP) family of ICs, such as ICP2, ICP3 and ICP4 on design (Interlaced HDR, Pixel Mixer), functional verification, Static Timing Analysis, and power estimation/optimization• Mass production support for Automotive backup camera SoC (ASX343) (stuck-at, and at-speed DFT improvements, functional validation)

Bangalore

• Design Architect and Program Manager for Software Defined Radio comprising ARM1176, ARC710, and CEVA DSP processors• Lead role in development and production support for Cortex R4 ARM processor based MCUs for Fujitsu, Germany• Business, customer front-end, and technical proposal development culminating in > 2M$ revenue, and more than 5 key project wins• Drove digital solutions growth strategy and implementation working with multiple cross functional teams

Bangalore

• Contribution to multiple generation of successful WiMAX SoCs• Designed and integrated DDR (LPDDR1 and DDR2) controller, Power Management Controller/Power Management Unit (PMU), Cardbus/PCI controllers on WiMAX baseband devices• ASIC Lead for WiMAX CPE products based on Multi-Chip Module comprising WiMAX SoC, Network Processor, and DDR die• Support for ISO 2001 certification and development of quality management system leading to successful ISO certification

Program Manager/Technical Lead for optical mouse digital chip. Led an 8-people team from product specification to tapeout including proof-of-concept FPGA prototypingTechnical lead for BIST and test logic of Network Search Engine families. Led a 3-member team for developing Mem-BIST, I/O BIST, JTAG and other test logic.Block design of Virtual Concatenator RX for 2.4 Gbps OC48 framer family.

Master Of Business Administration (M.B.A.), Business Administration And Management, General

Activities and Societies: General MBA at U21 Global/Univ of Melbourne

B.Tech, Electronics And Communication Engg.

University 2nd rank

Higher Secondary, Physics, Chemistry, Mathematics

Education record