Govind Mantri Email & Phone Number

Bengaluru, Ka, In

Bengaluru, Karnataka, India

• Tapeout for next-generation transceiver chip with O-RAN: RTL-to-GDS ownership for following subblocks. Additional support on constraints closure, design feedback, STA timing closure, PV analysis,checklist bring-up etc.1. ORAN block: Challenges: 85%+ memory dominant block with various sub-hierarchies instantiatedwith 60% final density. Multiple feedthroughs, high-speed design, timing closure.2. L4 block: Challenges: 90%+ memory dominant block, rectilinear floorplan to accommodate top-levelrequirements with in-power/area focus.• Tapeout for 8T-8R transceiver chip on 16nm: Netlist-to-GDS ownership for following sub-blocks.1. JESD block: Challenges: Multi-clock design, Inter-clock skew and hold, SERDES routing, cross-talkand addressing performance bottle-necks.2. Carrier Digital Up-converter block: Challenges: Min-power/area opti., pipelines feedback.• Revision tapeout for a previous chip by implementing ECOs on a post-route DB.• Bench-marking new technology node and identifying future challenges on 5nm to understand trade-off between design requirements & cost for process parameters like VT selection, metal-stackselection, PPA uplift etc.

Bengaluru Area, India

• Octa-core top-level implementation on 5nm:· Implemented an octa-core cluster for a premium spec having big, medium & little core configuration with Cortex-A55+Cortex-A76.· CPU shape, size & aspect ratio was modified to fit like a jigsaw puzzle to push area optimization for a high system performance. Crosstalk analysis and mitigation techniques like layer promotion, congestion & routing analysis etc. were used to push performance.· Configuration of the design was picked by throughput & DVFS analysis of the cores.· Robustness of design was improved by performing & analyzing quality-checks like LEC, IR drop, DRC analysis, CLP.• Top-level implementation of Cortex-A53 & Cortex-A73 on 12nm:· Achieved Min-area/leakage implementations for medium performance target specifications and signoff checks were performed to improve the quality metrics of the design.• Implementation of a low-power/min-area of Cortex-A55 with a prime focus on Dynamic power which was improved by 15% by using techniques like MBFF optimisation, area reduction, clock tree optimization selective selection of IPs on 11nm.• Developing register-file memory compiler on 11nmWorked on developing memory compilers for 11nm and exploring memory development flows like cleaning margins, characterization & its verification, Front-end package checks etc.

Bengaluru Area, India

High performance implementation of Cortex-A75 tuned for area budget was done on 11nm. Deep down analysis of dynamic power was done to improve clock switching power, macro power and flops internal power bringing down the overall dynamic power by 15%

Bengaluru Area, India

Worked on cluster level implementations for different big.LITTLE octa-core configurations at different FINFET technology nodes like 16, 10. Also worked on CPU implemenattions for Cortex A-55 & Cortex A-75 on 10nm.

Noida Area, India

I was a summer trainee in the BOE department at Videocon d2h for one month. I learnt about the broadcasting and engineering operations in the DTH industry during this period.

Trivandrum