Greg Burda Email & Phone Number

Raleigh, Nc, Us

Redmond, Washington, Us

Director of circuit and CAD/EDA team designing memory and foundational IPs for a broad range of compute and AI products. Custom memories, DTCO stdcell, clocking circuits, storage elements, structured datapath, testchip design on multiple process nodes with full RTL-to-GDS responsibilities and more. CAD/EDA teams develop methodologies for simulation, LPE, physical verification, timing, functional verification, infrastructure, etc. Created scalable architecture for advanced process node testchips and led teams performing RTL, DV, PD, circuit, board & package, and post-silicon characterization.

San Diego, Ca, Us

Manage a team of 40 custom digital circuit, methodology, post-silicon characterization, and mask layout designers in the development and productization of high-performance, low-power mobile (Snapdragon) and server (Centriq) products. All products demonstrate industry-leading power-performance metrics. Team has designed custom SRAM, custom and compiler register files, CAMs, pulse latches and stdcell libraries in technologies ranging from 45nm to 7nm with performance up to 3GHz+.Drive team members to the on-time delivery of circuit deliverables such as LIB, LEF, GDS, APL, CMM. Ensure high-quality, error-free delivery through the development of a detailed and thorough release checking system. Able to quickly react to technology PDK revisions with little-to-no schedule impact.Circuit techniques include custom single Vdd bitcell design, 6T/8T/10T SRAM memory arrays, read/write assist, static/dynamic comparators, multi-Vdd domains, single-ended/differential sensing, low-skew clocks. Performed PPA evaluations of various stdcell library architectures across multiple technologies.Work closely with foundry suppliers on new circuit technology initiatives such as diffusion-bridged libraries, custom single Vdd bitcells, groundrule relaxations, yield improvements. Designed and did post-silicon characterization of testchips for next-generation CPU and technology development. Post-silicon test team tasks included development of random instruction generator, targeted vectors, debug of Vmin-limiting paths, triage and debug of RMAs, work with foundry and process team on DLY and PLY detractors. Methodology team supports simulation environments, timing and power characterization, and Cadence tool suite, PDK. High-sigma statistical analysis, Hspice, Hsim, Finesim. Various custom methodologies written to support circuit team.Mask layout design team for custom digital and analog circuits. Attention to LDE, yield detractors, layout efficiency, DFY/DFM.

San Diego, Ca, Us

Lead custom circuit designer for multi-port CAM-RAM used as part of Execution Unit Register Renaming Scheme. Fully-associative CAM-RAM with multiple tag-write ports, CAM search ports, RAM read ports. Schematic and layout entry in 45nm, 65nm, and 90nm process technologies. Designed CAM bitcell with read ports, row/column circuitry, decode, matchline hierarchy, input/output latches. RAM bitcells, read precharge/evaluate circuits. Write-through-read comparators and bypass circuitry. Performed Hspice/Hsim circuit analysis. Supported BIST testplan and ATPG scan methodologies.Layout tasks included floorplanning, wire track planning, noise shielding considerations, power grid, transistor-level layout. DRC/LVS/ERC, antenna checks.Schematic-to-RTL verification with ESPCV symbolic checks, functional SLS, BIST SLS. Statistical analysis for bitcell write-ability, read, keeper sizing.Interfaced with process technology team on technology issues related to CPU low-Vt transistors, bitcells, spice models. Worked with team to develop a principal-component variation model for statisical analysis.

Armonk, New York, Ny, Us

Custom circuit design engineer for embedded microprocessors. Performed full-custom digital design for multi-port register files. Read/write decode, bitcell design, local-to-global bitline design, scan test methodology. Also performed mask layout design for register files in 90nm, 130nm, 180nm technologies. Supported in-house parasitic extraction methodologies, batch submission jobs. Shell script and GUI for job submission. Performed various debug and support of RC and device extraction issues.Spearheaded efforts for custom macro design team to use in-house formal verification for schematic-to-RTL equivalence checking. Also moved team into Innologic symbolic verification engine for schematic-to-RTL equivalence checking.

Armonk, New York, Ny, Us

Worked in EDA team charged with developing in-house device-level parasitic extraction tool (ERIE). Created layout testcases and performed HSPICE benchmarking analysis of ERIE vs. 3-D field-solver extractions.