Greg Kurtz

Greg Kurtz Email and Phone Number

PCB Design Engineering Lead at Google @ Google
Mountain View, CA
Greg Kurtz's Location
Mountain View, California, United States, United States
Greg Kurtz's Contact Details

Greg Kurtz personal email

About Greg Kurtz

Greg Kurtz is a PCB Design Engineering Lead at Google at Google. He possess expertise in pcb design, rf, schematic capture, design for manufacturing, signal integrity and 5 more skills.

Greg Kurtz's Current Company Details
Google

Google

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PCB Design Engineering Lead at Google
Mountain View, CA
Website:
google.com
Employees:
1
Company phone:
916.253.7820
Greg Kurtz Work Experience Details
  • Google
    Pcb Design Engineering Lead
    Google Jan 2021 - Present
    Mountain View, Ca, Us
  • Microsoft
    Sr Pcb Designer
    Microsoft Apr 2019 - Jan 2021
    Redmond, Washington, Us
    Sr PCB Designer - HoloLens - Responsible for the design of Main Logic Board, Development Boards, and FPC Designs for Microsoft HoloLens
  • Google
    Cad/Pcb Design Engineer
    Google Oct 2017 - Apr 2019
    Mountain View, Ca, Us
    • Responsible for the design of Main Logic Board and FPC designs for Pixel Phones. • Perform constraint driven digital, analog, and RF layouts with HDI technology, high density 0.35mm pitch BGA's, controlled impedance, high-speed clocks, differential pairs, design for manufacturability and design for test. • Layout Design Lead for the Pixel 3. Launched October 2018.• Most recent stack-ups used: 12 Layer ELIC (Every Layer Interconnect) 3, 4 and 5-layer FPC designs.• Responsible for valor checks, documentation, and design release to PCB vendors.• Implemented PCB design process for Phone Group.• Implemented DFA rules improving component placement density on MLB’s.• Work closely with fabrication and assembly vendors for quality and new technology implementation.• Design tools: Cadence Allegro v17.2, Valor, G Suite, Git
  • Microsoft
    Sr Pcb Designer
    Microsoft Nov 2014 - Oct 2017
    Redmond, Washington, Us
    Sr PCB Designer - HoloLens- Responsible for the design of Main Logic Board, Development Boards, and FPC Designs for Microsoft HoloLens Product. - Perform constraint driven digital, analog, and RF layouts with high density 0.4mm pitch BGA's, controlled impedance, MIPI, high-speed clocks, and differential pairs.- Most recent stack-ups used: 12 Layer ELIC (Every Layer Interconnect) 3, 4 and 5 layer FPC design.- Responsible for valor checks, documentation, and design release to PCB/FPC vendors.- Train and assist PCB Designers and EE’s with the Allegro and the PCB Process. - Achieved increase in productivity by implementing custom hot keys. - Work closely with DFx teams to produce cost effective, high quality PCB’s and FPC’s- Design tools: Cadence Allegro v16.6, Valor NPI v9.5
  • Apple
    Sr Pcb Designer
    Apple Aug 2014 - Nov 2014
    Cupertino, California, Us
    Sr PCB Designer Engineer - iPhone- Responsible for the design of Main Logic Boards and Development boards for Apple iPhone. - Perform constraint driven digital, analog, and RF layouts with high density 0.4mm BGA's, controlled impedance, high-speed clocks, differential pairs, and design for manufacturability. - Assist PCB Designers in the resolution of critical design problems. - Train PCB Designers in specialized areas of PCB design.- Propose PCB design trade-offs to the engineering design team for resolution and implementation.- Design tools: Cadence Allegro
  • Wistron Mobile Solutions
    Pcb Designer
    Wistron Mobile Solutions Jan 2013 - Jul 2014
    Sr PCB Designer- Responsible for the design of Main Transceiver PCB’s for Blackberry 10 product. - Perform constraint driven digital, analog, and RF layouts with high density .4mm pitch BGA's, controlled impedance, high-speed clocks, differential pairs, and design for manufacturability. - Perform placement and routing feasibility studies.- Work with PCB Vendors to design stack-ups. Most recent stack-up used for Main XCVR PCB: 10 Layer ELIC (Every Layer Interconnect), - Perform documentation and design checks using Valor.- Perform impedance control calculations using Polar. - Responsible for designing manufacturing panel and panel optimization for a cost effective solution. - Responsible for Mentoring PCB Designers and EE’s with Cadence tools.- Design tools: Cadence Allegro,OrCADCapture, Zuken CR5000, Valor,Polar
  • Blackberry
    Pcb Designer
    Blackberry 2008 - Jan 2013
    Waterloo, Ontario, Ca
    Sr PCB Designer/PCB Team Lead- Responsible for the design of Main Transceiver PCB’s for Blackberry 10 and BlackBerry Curve Products. - Perform constraint driven digital, analog, and RF layouts with high density .4mm pitch BGA's, controlled impedance, high-speed clocks, differential pairs, and design for manufacturability. - Perform placement and routing feasibility studies.- Work with PCB Vendors to design stack-ups between 2 and 12 layers. Most recent stack-ups used for Main XCVR PCB: 10 Layer ELIC (Every Layer Interconnect)- Perform documentation and design checks using Valor.- Perform impedance control calculations using Polar. - Responsible for designing manufacturing panel and panel optimization for a cost effective solution. - Prepared required documentation for QMS ISO Audit for BlackBerry products. Interviewed by ISO Auditor, passed audit and best practices were added to BlackBerry design process.- Trained PCB Designers and Engineers on Design Change Tracking System for ISO process which is now implemented at all BlackBerry sites.- Achieved an increase in productivity by writing scripts to improve design software. - Responsible for Mentoring PCB Designers and EE’s with Zuken tools.- Design tools: Zuken CR5000, Valor, Polar, Mentor Graphics Board Station
  • Motorola
    Pcb Designer
    Motorola 2000 - 2008
    Sr PCB Designer- Responsible for designing the Main Transceiver PCB for multiple products including the 3G Razr for North America.- Design layouts using HDI technology on stack-ups with 4 to 12 layers- Perform complex digital, analog, and RF layouts with high density BGA's, controlled impedance, high-speed clocks, and design for manufacturability. - Perform documentation and design checks using Valor. - Responsible for beta testing new software releases.- Worked on a team to streamline the PCB design process.- The creation of geometries, schematic symbols, mapping files, and catalog entries for the Master Component Library
  • Plexus Technology Group
    Pcb Designer
    Plexus Technology Group 1997 - 2000
    Neenah, Wi, Us

Greg Kurtz Skills

Pcb Design Rf Schematic Capture Design For Manufacturing Signal Integrity Wireless Cadence Hardware Architecture Embedded Systems Hardware

Greg Kurtz Education Details

  • Fox Valley Technical College
    Fox Valley Technical College
    Electronics Technology
  • University Of Wisconsin Oshkosh
    University Of Wisconsin Oshkosh

Frequently Asked Questions about Greg Kurtz

What company does Greg Kurtz work for?

Greg Kurtz works for Google

What is Greg Kurtz's role at the current company?

Greg Kurtz's current role is PCB Design Engineering Lead at Google.

What is Greg Kurtz's email address?

Greg Kurtz's email address is gk****@****hoo.com

What schools did Greg Kurtz attend?

Greg Kurtz attended Fox Valley Technical College, University Of Wisconsin Oshkosh.

What skills is Greg Kurtz known for?

Greg Kurtz has skills like Pcb Design, Rf, Schematic Capture, Design For Manufacturing, Signal Integrity, Wireless, Cadence, Hardware Architecture, Embedded Systems, Hardware.

Who are Greg Kurtz's colleagues?

Greg Kurtz's colleagues are Özlem Geyik Özmen, Дмитрий Пономарёв, Nuria Penélope Herchiga Martin, Nikhil Bakshi, Bethany Taylor, Sarah Tama, Miret Guillaume.

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