Greg Starr Email & Phone Number

Palo Alto, California, Us

San Jose, Ca, Us

Responsible for the delivery of advanced IP for Hard Disk and Tape Drive PreAmps. This is an exciting field because it involves hard core analog design on advanced biCMOS processes. Circuit performance and speed is truly cutting edge and represents some of the most challenging design work around. Specific responsibilities include:- IP and Technology roadmap to support emerging needs of the disk drive industry on advanced SiGe BiCMOS process- Project management of three major parallel developments- Multi-site management- Organizational goal setting and tracking- Development methodology- Software development for metric tracking- Software specification development for productivity increasing tools

Design Director responsible for reconfigurable serial IO on the most advanced CMOS processes. Protocols supported include PCI Express gen 1 2 3, XAUI, 10G Ethernet, OIF CEI-6G, Interlaken, Gigabit Ethernet, OC-192, OC-48, OC-12, OC-3, OTU-1, OTU-2, OTU-4, serial RapidIO, CPRI 9G, CPRI, OBSAI, HD-SDI, DisplayPort, Serial ATA, Fibre Channel, SAS, Infiniband, GPON, 10G BASE KR, CEI-11, and SFP+. This role involved working with customer marketing on the product definition; planning projects for execution; establishing design methodology; defining, reviewing, and executing verification plans; establishing tracking metrics. Responsible for building team from 6 designers to over 20. Staffed managers and created well defined groups for clarity of ownership. Successful project taped out on 90nm, 65nm, 40nm, and 32nm CMOS processes.

Santa Clara, Ca, Us

Responsible for full chip architecture of a family of novel programmable logic devices using dynamic reconfiguration. Responsible for detailed architecture definition including floorplanning of the entire product line. Architecture modeling in Verilog for accurate emulation of the design. Architectural exploration to meet customer needs. Interfaced with outside IP providers to manage delivery of key mixed signal blocks.

San Jose, Ca, Us

Responsible for all full chip timing elements within Xilinx FPGAs which included the global clock network, DLLs, and PLLs. Responsible for driving Xilinx's first generation integrated PLL for Virtex 5 and Virtex 6. Responsible for driving removal of the DLL for Virtex 7 by developing a novel approach for mapping DLL applications into the PLL. Drove resolution of several major issues on Virtex 4 which resulted in significant yield improvement. Reponsible for driving Monte Carlo analysis into Xilinx which is now the de facto standard within the company for ensuring a robust design.

Responsible for a wide range of tasks with an every increasing degree of responsibility. Owned all core PLL development for APEX II, Stratix, and Stratix II families of FPGAs. All products are in full scale production. Specific ownership included architectural definition, design, layout oversight, and pre-tapeout verification. Maximum frequencies up to 1.6GHz. PLL architectural investigation performed using custom C++ code, Matlab, and Simulink. Responsible for the development of the indutries 1st fully integrated DSP core building block for FPGAs. Worked directly with DSP architect to perform trade-off studies of various architecture to identify trade-offs between power, area, and features. Block is now a standard offering on virtually every FPGA across the entire industry. Also responsible for the high speed parallel interface block on Stratix II. Interface block included high serial to parallel and parallel to serial conversion block, FIFO, and per bit dynamic clock alignment circuit. Block intended for use with high speed parallel IO standards like HyperTransport, SPI 4.2, SFI-4, XSBI, RapidIO, NPSI, and Utopia IV. Owned full chip clock network architecture, design, layout oversight, and pre-tapeout verification. Clock networked designed to be scalable across entire product family. Also responsible for the 90nm IC design simulation models. Developed robust flow for mapping TSMC models into Altera design simulation models, running pre-release verification, and quantifying the differences between model releases to ensure model quality. Worked directly with customers to understand their current and future needs to help drive feature enhancements.

Ch

Responsible for analog IC design on CMOS and BiCMOS processes for power management including linear regulators and switched regulators. Also responsible for quad pin driver for Teredyne testers for IC tester application. Responsible for circuit architectural development, detailed transistor level circuit design, verification planning and executions for all modes of operation and PVT corners, Created various software tools for mapping netlist between various simulators to speed up circuit translation. Created area estimation tools to provide approximate die size estimates ahead of layout to enable design optimization while minimizing die size. All software written in C++.

Santa Clara, California, Us

Responsible for development of various components used in digital cameras. Resposible for ASIC architecture, specifically with defining a generic interface to LCD modules, analysis of florescent light induced flicker on pipelined CMOS sensors. Modeling included full system to enable prediction of end customer experience. Identified novel method for detecting frequency of flicker and subsequent sampling timing to enable removal of the aritifact. Characterized the range of flicker induced light modualtion to enable accurate modeling of the level of the artifact. Two patents granted from the work. ASIC architectural studies performed using C++ modeling to predict bus loads under various customer use cases to ensure sufficient bandwidth and bus scheduling prioritization.

Charlotte, North Carolina, Us

Design aircraft avionics and test systems for business and commuter aviation. Successfully released two major avionic suites into production. New test platform released into factory and field which enabled high coverage of products. Training modules developed and provided to factory and field technicians to ensure they were able to successfully use test platform.- Plan, architect, and implement product test strategy for aircraft avionics to ensure product quality.- Develop embedded firmware for Intel based x86 processors in assembly to support production test- Develop C-programs for test systems control to ensure complete testing of products before release to customers- Board level analog and digital design including programmable arbitrary waveform generators, dual channel digital oscilloscope, programmable high current drivers and loads- FPGA design for system control in Verilog.- Board layout including signal integrity analysis.

Mse & Phd, Semiconductor Device Physics, Opto-Electronics, Ic Design, Asic Design, Analog Ic Design

Bs, Electrical Engineering