Greg Starr Email & Phone Number

Palo Alto, California, US

San Jose, CA, US

Responsible for the delivery of advanced IP for Hard Disk and Tape Drive PreAmps. This is an exciting field because it involves hard core analog design on advanced biCMOS processes. Circuit performance and speed is truly cutting edge and represents some of the most challenging design work around. Specific responsibilities include:- IP and Technology.

Design Director responsible for reconfigurable serial IO on the most advanced CMOS processes. Protocols supported include PCI Express gen 1 2 3, XAUI, 10G Ethernet, OIF CEI-6G, Interlaken, Gigabit Ethernet, OC-192, OC-48, OC-12, OC-3, OTU-1, OTU-2, OTU-4, serial RapidIO, CPRI 9G, CPRI, OBSAI, HD-SDI, DisplayPort, Serial ATA, Fibre Channel, SAS, Infiniband.

Santa Clara, CA, US

Responsible for full chip architecture of a family of novel programmable logic devices using dynamic reconfiguration. Responsible for detailed architecture definition including floorplanning of the entire product line. Architecture modeling in Verilog for accurate emulation of the design. Architectural exploration to meet customer needs. Interfaced with.

San Jose, CA, US

Responsible for all full chip timing elements within Xilinx FPGAs which included the global clock network, DLLs, and PLLs. Responsible for driving Xilinx's first generation integrated PLL for Virtex 5 and Virtex 6. Responsible for driving removal of the DLL for Virtex 7 by developing a novel approach for mapping DLL applications into the PLL. Drove.

Responsible for a wide range of tasks with an every increasing degree of responsibility. Owned all core PLL development for APEX II, Stratix, and Stratix II families of FPGAs. All products are in full scale production. Specific ownership included architectural definition, design, layout oversight, and pre-tapeout verification. Maximum frequencies up to.

CH

Responsible for analog IC design on CMOS and BiCMOS processes for power management including linear regulators and switched regulators. Also responsible for quad pin driver for Teredyne testers for IC tester application. Responsible for circuit architectural development, detailed transistor level circuit design, verification planning and executions for all.

Santa Clara, California, US

Responsible for development of various components used in digital cameras. Resposible for ASIC architecture, specifically with defining a generic interface to LCD modules, analysis of florescent light induced flicker on pipelined CMOS sensors. Modeling included full system to enable prediction of end customer experience. Identified novel method for.

Charlotte, North Carolina, US

Design aircraft avionics and test systems for business and commuter aviation. Successfully released two major avionic suites into production. New test platform released into factory and field which enabled high coverage of products. Training modules developed and provided to factory and field technicians to ensure they were able to successfully use test.

Mse & Phd, Semiconductor Device Physics, Opto-Electronics, Ic Design, Asic Design, Analog Ic Design

Bs, Electrical Engineering