Greg Tse Email & Phone Number

Santa Clara, California, Us

Successfully contributed in design of many IC products. Intel's 1st ARM XSCALE CPU product: Worked on L2 cache and system bus interface design of 1st Intel ARM base CPU. Arm based storage IO processor: Designed DMA controller with RAID5/6 support and Block Protection Technology (BPT) support. SAS/SATA storage controller units (PCH): Designed complex link-list based DMA block to support 8 lanes at 12Gb/s. Arm based media processor: Designed Video memory controller hub and XSCALE memory hub. Atom CPU: Designed DFX features: RCOMP, boundary scan, VISA, and ACIO loopback. Atom base MicroServer SOC: tool flow methodology and system integration of soft and hard IP.

PowerPC Northbridge chipset: Designed PowerPC Slave, PCI master and PCI Arbitration block of the PCI host bridge. Developed Verilog fullchip testbench and fullchip directed/random tests. synthesized and resolved timing closure for designed blocks.Supported Quickturn Emulation and initial chip bringup.PowerPC to VME bus bridge: Intial testbench development. Coded VME master/slave Bus Functional model including 2eVME and 2eSST support.Designed Motorola first MAC cloned Common Hardware Reference Platform. support windowNT, LINUX and MacOS boot.

Us

PCI Block MUX Controller: Designed i960 base PCI Block MUX Controller using PLDs.VME Block MUX Contoller: Designed i960 base VME Block MUX Controiller using PLDsQUAD 88100 CPU single board computer: Designed DDR interface and VME interface using PLDsResponsible for Schematic capture, placement/layout, prototype debug, and system bringup.