Greg Davey Email & Phone Number

Rochester, Ny, Us

Rochester, Ny, Us

Melbourne, Florida, Us

• Participated in subsystem design for synthesizer RF electronics and signal processor digital electronics for active electronically scanned array (AESA) radar.• Designed and implemented chiplevel system for radar system FPGAs tasked with synthesis of agile LO, ECCM adaptive processing, digital beam forming, and coherent processing.• Designed and implemented single precision electronic countercountermeasure (ECCM) adaptive processor for use in modern AESA radars. This solution was proven extensible to provide realtime spacetime adaptive processing (STAP) capabilities in current FPGA technology.• Designed and implemented low phase noise agile LO used in new Lband phased array radars.• Provided analysis and guidance for re-architecture of various radar subsystems to comply with DAU's Open Architecture initiative as well as the US Navy's Digital Array Radar (DAR) Open Interface Requirements Specification.• Assisted business development group as technical resource by performing notional system level design for capability enhancement and life extension of existing radars for both domestic military customers and foreign military customers restricted by International Traffic in Arms Regulations (ITAR).• Provided engineering support for the US Marine Corps during Joint Distributed Engineering Plant (JDEP) test events of the AN/TPS59. These test events required simulated air-breathing targets (ABTs) and theater ballistic missiles (TBMs) to be locally injected into the radar and received by the remote Tactical Air Operation Module (TAOM).• Managed Saab Sensis' Seaport Enhanced multiaward contract for development of new engineering services opportunities with the US Navy's virtual commands including NAVAIR, NAVSEA, and SPAWAR, as well as with the US Marine Corps.• Assisted in technical writing for proposal effort of a new expeditionary long range AESA for the USAF, including portions of the system architecture and reliability and maintainability program plan.

Amherst, New York, Us

• Designed multi-GHz circuits and printed circuit boards for ATTO's high performance storage systems. These products used highspeed serial interconnects, e.g., 10Gb Ethernet, 8Gb FC, PCIe 2.0, SAS 2.0 and SATA, to rapidly move large amounts of data.• Performed duties as Hardware Technical Lead. These duties included scheduling project resources, drafting the Hardware Design Specification, ensuring proper component derating, completing power estimates, preparing thermal estimates and tests, calculating reliability estimates (Bellcore TR332), drafting Design Verification Test documents, and coordinating FCC and CE compliance for emissions, ESD, and immunity.• Synthesized HDL designs targeted to Altera and Xilinx FPGAs.• Created reusable programmable clock and power designs to reduce cost and PCB real estate.• Worked with executive, marketing, operations, purchasing, and sales teams to fulfill functional requirements, mitigate risk, and prepare for large scale production and testing of new designs.• Performed Reliability Engineering study on current design processes and implemented a Failure Modes, Effects and Criticality Analysis (FMECA) procedure. Designed additional procedures, including Failure Reporting, Analysis, and Corrective Action System (FRACAS), Reliability Demonstration Testing (RDT), and Ongoing Reliability Testing (ORT).• Determined requirements of National Institute of Standards and Technology (NIST) Federal Information Processing Standards (FIPS) Publication 1402 Security Level 3 for data storage products using encryption. Provided recommendations for anti-tamper (AT) and physical security to meet the requirements of the standard.• Implemented finite field algorithms in VHDL and Verilog for use in IEEE P1619 compliant encryption, RAID6 utilizing ReedSolomon codes for Q parity generation, and random number generation.

• Maintained and optimized a proprietary realtime operating system for use in modems, facsimile machines, and VoIP systems.• Maintained a μClinux variant on the MIPS architecture for an enterprise VoIP bridge.• Assisted in implementation and optimization of various ITU-T G series audio codecs in C, C++, and assembly.• Developed reference design schematics for mixed signal appliances based on DSPs from Analog Devices and Texas Instruments.• Assisted with design and implementation of a 900 MHz handheld radio in cell phone packaging using a FSK modulation scheme.• Reviewed reference design layouts.• Coordinated prototype manufacturing of reference designs.

Washington, Dc, Us

4 Years active duty plus 4 years reserve.

Bs, Electrical Engineering

Bs, Computer Engineering