Greg Holdren Email & Phone Number

Sacramento, Ca, Us

Rancho Cordova, Ca

- VHDL code development for FPGA/CPLD based control for elevator safety and monitoring using car, motor and hoistway IO inputs along with CAN communication interface designs.- Designed Linear and switching power supplies with PMIC and linear solutions.- Designed with STM32, PIC microcontrollers in various CAN controlled auxiliary IO boards.- Analog interfacing with and without A/D and D/A, Motor brake IGBT protection circuits.- Schematic and PCB layout, stack-up planning and signal integrity simulation and measurements.- Board bring-up and validation for functionality and AC/DC performance.- New and EOL (End of Life) component selection.- Interface with production, materials and purchasing.- Scripting languages for internal/external tools.

Roseville, California

Developed python test code in the classifier team for Access Control List (ACL) and policy tests on network router/switches.

Folsom, California

- Developed regression test software to test Micron RealSSD Enterprise PCIe and Micron/Crucial Client SATA SSD drives using C/C++. Tested releases consisting of FW, Windows/Linux drivers and SSD management API library. Regression test automation using Jenkins to test ~100 Windows and Linux servers.- Wrote tests to exercise and inject MSE (Micron Storage Executive) API and VU (OEM Vendor Unique) API calls while running various IO loads and types.- Maintained and developed test libraries such as threaded AIO workers, Sleep state code, CuTest, Variable IO worker modes, Read and Write latency tracking, Write cache flushing, IOCTL calls etc. to aid in stress testing SSDs.

Roseville, California

- Validated PMC-sierra SRC 6G SAS RAID PCIe controller. Validation of Firmware, Linux and Windows drivers and RAID management CLI /GUI components for SRC card.- Test plan development to cover RAID and drive configurations with both rotational and flash based SAS and SATA drives. Developed battery backup tests to ensure correct RAID card operation and proper CLI/GUI reporting of battery state.- Used TCL and Tk to write upper level user GUI to characterize ONFI/Toggle flash on an embedded host platform.- Maintained server racks and network infrastructure for test servers. Maintained file server for test support.

Roseville, California

- Maintain and support system firmware test code for the Itanium based Integrity Servers in the System Firmware team using Expect, Tcl, Perl and C. Added new tests into Integration Stress Test (IST) with increased test coverage needs.- Create test plans and test cases for new system firmware code base.- Wrote positive and negative test cases for UEFI shell commands, memory subsystem and backplane bus error injection testing.

Roseville, California

-Designed network PC LAN EISA, ISA, PCI and MCA adapter cards for PC compatibles desktops/servers and HP UNIX workstations. Designed Jetdirect EIO and LIO printer networking cards and modules for Jetdirect enabled printers. Other IO connectivity HW such as USB and IEEE1394 Firewire interfaces included for connectivity interfaces.-Designed FPGA and ASIC test PCBs for in house experiments/testing and pre-product development boards in addition to final production boards. Selected pin placement maps for ASIC and FPGA ICs based on product design needs.-Integrated LAN HW on the printer formatter PCB for Laser and Inkjet printers. Provided technical HW support for other printer divisions that later integrated LAN onto the printer formatter.- Responsible for test setup and monitoring of regulatory and environmental testing in HW test center. Report issues and worked with test center techs for RFI, radiated and conducted EMI, ESD tests as well as environmental tests such as temperature, humidity and altitude chambers etc. Worked with EMI and other design engineers and including test center techs to address issues and provide counter measures with conducted, radiated EMI and ESD failures.-Tested network physical interfaces to ensure IEEE spec conformance for 10/100 Mbit/s (10BaseT/100BaseTX) and 1 Gbit/s (1000BaseTX) using Tektronix solution and with in house HW. Measured ISA, EISA, PCI and memory bus AC/DC parameters to ensure ASIC/FPGA conformance to appropriate bus spec.-Provide technical support for in house and overseas product builds for manufacturing and mechanical. Work with procurement to find alternate electronic components for new designs or alternative second sources.-Modified Printer LAN driver to select 10/100 Mbit/s MAC or 1 Gbit/s MAC based on link state from PHY.-Printer performance testing with different real world software applications.

Roseville, California

- Supported lab engineers with FW upgrades and HW mods. Built prototype boards for HW experiments and SW testing. Aided in board bring up and test.- Test network physical interfaces to ensure spec conformance. Measured ISA, EISA, and PCI bus AC/DC parameters to ensure ASIC/FPGA conformance to appropriate bus spec.- Responsible for test setup and monitoring of regulatory and environmental testing in HW test center. Report issues and worked with test center techs for RFI, radiated and conducted EMI, ESD tests as well as environmental tests such as temperature, humidity and altitude chambers etc.. Worked with engineers and test center techs to fix issues and retest.- Interface with various areas such as ICT, Process and Manufacturing. Provide support for proto and pre-production PCB/assembly builds.- Aided engineers with schematic entry for EISA based network adapters for PCs and HP UNIX workstations.- Participate in design reviews.- Maintained DOS16 TSR C based debugger tool for supporting all of the current and new additions of HP LAN cards (ISA, EISA, PCI and MCA buses) Used for Novell DOS ODI and Windows NDIS drivers development and provides displaying of register states, packet memory and rd/wr configuration of the controller's serial EEPROM.- Network topology and performance testing.

Roseville, Califormia

- Repaired functional bench failures in manufacturing and repaired field returns consisting of network StarLAN1, 10 and 10BaseT hub/concentrators and MAUs.- Defect analysis for component failure trends and manufacturing issues.- Went on several lab loan assignments to RND (Roseville Networks Division) R&D lab to support new product development and transfers to manufacturing.

Sacramento, California Area

Repaired test handlers consisting of MCT and Thermonics. Repaired IC testers consisting of LTX, MCT, Accutest and Teradyne systems. Mil spec ICs tested: 5400 logic, analog, and VLSI ICs (68K and 8031 CPUs ).

Santa Clara And Folsom, California

Repaired wafer probers consisting of Pacific Western Systems and Electroglass; IC handlers consisting of MCT and Delta. Repaired and calibrated test systems for EPROM and EEPROM memories testing. Repaired internally developed Intel S91 wafer sort tester. External testers consisting of MegaTest and Teradyne for final test.

Computer Engineering

As, Digital Electronics