Gregory Knight Email and Phone Number

Altera Cyclone V SoC FPGA development:- RTL (SystemVerilog) designs targeting Cyclone V SoC and Stratix V FPGAs- Implemented IEEE 1588 PTP (Precision Time Protocol) Timestamp support for system synchronization and data packet sequencing- Implemented remote image update using EPCQ Flash and Micron Flash devices- Implemented PCIe, SPI, I2C interfaces- Wrote python scripts for controlling external temperature sensors and power monitors- Supported ARM Cortex-A9 based HPS bring up with Cyclone V SoC.

• Architected and designed Hercules: an MDIO to I2C interface chip that facilitates indirect Read/Write access between a Broadcom switch and 12 SFP transceivers; an Ethernet Link and Activity LED status driver; a SW upgradable, self-reprogrammable, design with images stored in In-System Flash memory. Full chip design targeting a Xilinx Startan-3an FPGA. Built its testbench and BFMs. Test plan.• Architected and designed Newton: an asynchronous design, an Ethernet Link and Activity LED status driver. Full chip design targeting a Xilinx CoolRunner II CPLD. Built its testbench with BFMs. Test plan.• Worked on Apollo: an EEPROM Controller for FPGA programming; an Altera Max II CPLD.• Optimized three FPGA designs to accelerate PCB bring-up and automate Mfg tests; Virtex IV FPGAs.• Implemented design for testability techniques to verify DRAM and SRAM during manufacturing tests.• Designed complex, Verilog, RTL modules: System Rate Limiter (per leaky bucket algorithm), Ethernet Flow Control (per IEEE 802.3x), 128x32 bit CRC Generator, XAUI Shim, Register File, MDIO Bus (per IEEE 802.3x), I2C Bus, DRAM (DDR2) Memory Tester, SRAM Memory Tester• Architected and designed Verilog based top-level and unit-level testbenches. Devised test plans.• Created a SystemVerilog based Load Balancer BFM, and SystemVerilog verification regression testcases.• Architected and designed an automated Python /TCL/IXIA based lab regression testbench for performance testing and release verification. Conducted said testing.• Implemented XAUI Shim pipelining strategy to remove clocks and increase small packet throughput.• Implemented flow control strategies in order to guarantee zero packet drops due to data path congestion.• Implemented an oversampling clock strategy to provide an asynchronous reset solution.• Performed failure analysis and remote manufacturing tests on DDR2 DRAM DIMMs.• Managed FPGA Lab Testing Environment and Equipment.

• Demonstrated formal verification using JasperGold Verification System to potential customers at DAC, DVcon, and Jasper headquarters.• Tested JasperGold for Open Verification Language (OVL) and SystemVerilog support.• Performed software testing and bug tracking.• Created and reviewed technical documentation.• Product manager for GamePlan Verification Planner product releases (v1.0, v1.1, and v1.2).• Developed product roadmap, devised development and release schedules, facilitated status meetings, provided feature requirements and specifications, conducted thorough testing, tracked and prioritized feature requests and bug resolutions.• Authored the GamePlan Quick Start User’s Guide and release notes.

• Performed design conversion from Xilinx Spartan IIE FPGA to Actel ProASIC3 FPGA for Audio over Ethernet application.• Modified Verilog RTL Design from a 32x32 channel design to an 8x8 channel design.• Performed functional verification using ModelSim simulator.

• Debugged customer designs by tracing schematics, RTL code and gate-level netlists.• Used Synplicity Synplify to synthesize customer designs to fit various Actel FPGAs.• Performed functional verification on customer designs using ModelSim simulator.• Performed Static Timing Analysis on customer designs to identify possible timing issues.• Supported device programming and board level debug using Silicon Sculptor II and FlashPro programmers, and Silicon Explorer II debugger.• Answered technical questions regarding Actel Antifuse and Flash based FPGAs.• Conducted preliminary failure analysis on FPGA devices at the board level.• Authored Application Notes and contributed to FPGA datasheet reviews.

• Maintained design units for PHY layer transceiver ASIC. IEEE 802.3ae 10Gb Ethernet specification (XAUI).• Performed synthesis and static timing analysis on SerDes control block.• Performed verification on SerDes Control at block and top levels through simulation.• Implemented soft reset functionality through MDIO and reset block; RTL coding.• Supported integration of 8b/10b encoder/decoder.• Wrote test cases to duplicate error conditions for Fast Infrared (FIR) Transceiver.• Ran Vera based testbench, Verilog testbenches and Perl scripts.