Gregory Walter Email & Phone Number

San Francisco, Ca, Us

Santa Clara, California, Us

San Francisco, Ca, Us

→ 𝗣𝗿𝗶𝗻𝗰𝗶𝗽𝗮𝗹 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿, FPGA, CloudManaged all aspects of hardware design, including roadmap and FPGA architecture, software compatibility, and development. Also responsible for cloud-based devOps tool product requirements and cloud resources.• Hardware Roadmap: Spec’d Xilinx Ultrascale+ FPGA on off-the-shelf, low-cost PCIe card to showcase Bayware Policy Engine switch, RISC-V-based technology.• FPGA Design: Hired, set up design flow (servers, Vivado, Mentor tools, GitHub), and oversaw implementation of major blocks to achieve packet processing in sim environment. Wrote RTL for Classifier block.• Cloud: Managed extensive AWS/GCP/Azure resources and requirements for Bayware’s devOps bwctl tool; performed software integration testing; wrote customer documentation and tutorials using Ansible, Python, and shell scripts.

Everycity, Oo

Developed web-based applications for small businesses including online payment gateway and in-take forms. Used latest industry tools for both backend design (Python plus lightweight CherryPy web framework) and frontend design (JavaScript, HTML5, CSS3, Bootstrap). Leveraged skills and understanding to more effectively design FPGA- and cloud-based networking products in subsequent position.

San Jose, Ca, Us

→ 𝗦𝗲𝗻𝗶𝗼𝗿 𝗦𝘁𝗮𝗳𝗳 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿, 𝗔𝗦𝗜𝗖 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴, 𝟮𝟬𝟭𝟯 – 𝟮𝟬𝟭𝟰Member of technical team with focus on next-generation products.• Lab Bring-Up: worked with internal board, diagnostic, and software teams as well as external ASIC foundry to prove functionality of new high-speed Ethernet switch chip.→ 𝗦𝗲𝗻𝗶𝗼𝗿 𝗠𝗮𝗻𝗮𝗴𝗲𝗿, 𝗔𝗦𝗜𝗖 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴, 𝟮𝟬𝟭𝟭 – 𝟮𝟬𝟭𝟯Manager responsible for HBA and Ethernet Adapter ASIC product line.• Brocade VP Excellence Award: for outstanding contribution while leading ASIC engineering team to successfully launch new HBA/NIC Adapter product.• Management: successfully led team of nine ASIC design engineers supporting existing products as well as new switch/router ASIC from concept to tape-out.• Software Modeling: designed and developed C++ model for new switch/router ASIC’s complex ingress and egress packet processing paths.→ 𝗦𝘁𝗮𝗳𝗳 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿, 𝗔𝗦𝗜𝗖 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴, 𝟮𝟬𝟬𝟰 – 𝟮𝟬𝟭𝟬Integral part of ASIC design team, delivering complex components for many networking adapter and switch/router products. Responsibilities included spec writing, micro-architecture, RTL, block-level verification, and lab bring-up.• ASIC Design: responsible for creating new ASIC block designs across many chips including implementation of FCP (SCSI over Fibre Channel) protocol in silicon, 10Gbps Ethernet MAC, cache controller, exact-match look-up engine, and others.• Bring-up Software: designed C/C++ based software application for bring-up validation of Adapter ASIC, which was leveraged by other engineers for follow-on chips.• ASIC Verification: created many block-level verification environments, cementing skills in C/C++ and scripting while always utilizing the latest technology from Perl and Verilog PLI, to Linux multi-threaded socket-based software designs, and finally System Verilog.

Us

→ 𝗠𝗮𝗻𝗮𝗴𝗲𝗿, 𝗛𝗮𝗿𝗱𝘄𝗮𝗿𝗲 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿𝗶𝗻𝗴, 𝟮𝟬𝟬𝟭 – 𝟮𝟬𝟬𝟰Responsible for delivering CoSine hardware. Managed team of up to 15 engineers covering all aspects of hardware design including FPGA design, board design and layout, mechanical design, and software driver and diagnostics.• Management: Gained significant people, time, and budgeting skills in project-lead and management positions. Project-lead responsibilities included managing RTL, verification, and software driver engineers working on multiple projects. Manager responsibilities included supervising a team of hardware and software engineers, planning future product development, staffing open positions, and maintaining spending within budget constraints.• Architectural Design: Managed design of complex network processor-based system with mechanical, hardware system, and software engineers. Through architecture design, spec writing, and implementation, gained understanding of IPSec, IKE, GigE, and SONET protocols as well as QoS, layer-2 and layer-3 header parsing, and traffic rate limiting.• FPGA Lead: Directed small team of engineers on architectural design and implementation of six next-generation media adapters required for switch/router product. FPGAs functioned to move traffic between proprietary switch fabric and GigE, ATM, POS, and HDLC Phys.→ 𝗛𝗮𝗿𝗱𝘄𝗮𝗿𝗲 𝗘𝗻𝗴𝗶𝗻𝗲𝗲𝗿, 𝟭𝟵𝟵𝟵 – 𝟮𝟬𝟬𝟬FPGA design engineer for networking and security products.• FPGA Design: responsible for design and development of complex Xilinx FPGA to support utilization of third-party security processing chips needed for quick customer deployment.• Verification: Developed chip-level simulation environments. Automated random test environments in Perl.• Software: Wrote board-level diagnostics including driver bring-up C code for several very complex third-party ASICs, involved writing chip initialization code as well as porting libraries.

Marlborough, Ma, Us

Member of hardware design team developing various networking router products. Significant responsibilities included ASIC & FPGA design and verification as well as several electrical board designs.

Msee, Electrical Engineering

Bsee, Electrical Engineering