I provide engineering consultancy services to clients for AdTech products.● Create, improve and maintain Demand-side Platform (DSP) components using C++ and Python;● Design features and integrations to third-party solutions to improve the client's current offering;● Create dashboards on Grafana and analyze metrics to substantiate technical decisions;● Debug and solve operational issues using logging data and metrics using Prometheus and Redash;● Improve deployment and feature quality by creating Unit tests in C++ and Python.

As a software engineer at Stellantis, I work on multiple architectures that impact vehicles worldwide.My main activities include:● Generating code via AUTOSAR methodology, using Matlab models and C/C++ code for software components;● Validating the code through unit tests, using C/C++ workbenches, Trace32 and Google Test;● Version management through git;● Developing tools and scripts in Python to automate tasks and provide clear data for data analysis and metrics activities.In addition, I work under Agile processes using the Scrum methodology, serving as the backup scrum master for my team.My contributions have helped achieve timely delivery of tasks during sprints, as well as improving existing processes and increase the efficiency within our teams.My proficiency in a range of programming languages and processes, allied with flexibility to take on new challenges, makes me an asset to teams looking for a dedicated and versatile professional.

I worked as a Software Developer on the architecture, UI/UX design and development of different projects, using several different languages. Some of these include: ● Nest.JS+Sequelize platform for integrating Bitrix CRM and PostgreSQL in a dockerized environment; ● React+DevExtreme website for portuary company; ● Static HTML+Jquery NativeFloripa Conference website; ● PHP+Rust paper appraisal platform for international conference;My role was to work and analyze our projects and make decisions with the team on how to improve our products and deliver them on time. My activities included:● Defining project requirements, target dates, tech stack and risks based on information from clients;● Structuring the relations between elements in the DB, defining and implementing tools using Docker, Nest.JS, Sequelize and PostgreSQL;● Creating optimal UX/UI strategies for naval platform while improving React/DevExtreme functionalities in the website;● Improving existing products using different APIs and functionalities, such as OAuth2, Bitrix24 and Whatsapp Venom;

I have worked in an Inference Accelerator project as part of the Design for Testability (DFT) team. I have performed the following activities:● Aligned the project activities flow for all DFT teams in the company;● Analyzed and implemented analog and digital test structures using Verilog;● Created scripts for activities using TCSH and TCL;● Managed the versioning and bug/ticket controls using Bitbucket, Git and Jira.● Generated and integrated the Boundary Scan structure using Siemens Mentor tools and Verilog;● Performed DFT DRC cleanup and generated mapped netlists via Genus Synthesis tools;

I have worked in i.MX RT500 and i.MX 8ULP projects. My roles were the following:● Designed test architectures for the chip, such as logical partitions, security and I/O pad distribution;● Integrated analog and digital structures in the chip using Verilog and VHDL;● Verified and fixed bugs together with Verification team, using C, Verilog and Agile tools;● Automated activities by using VBA, TCSH, BASH, TCL e PERL scripts.● Documented DFT functionalities and information using XML, directed at internal clients.● Communicated with and supported several different global teams to align and achieve multidisciplinary results;● Designed structures in Verilog to comply with security standards;● Performed hard chain stitching in memories and hardened blocks;● Tailored the simulation environment using TCL, PERL and TCSH towards project needs and debugged mismatches for SA and TD patterns;

Intern as Hardware Engineer in the SoC (System on Chip) Integration and Design for Test (DFT) teams. My activities were the following:● Designed the logical scan partition architecture for the chip;● Integrated analog and digital structures in the chip using Verilog and VHDL;● Verified and fixed bugs together with Verification team, using C, Verilog and Agile tools;● Automated activities by using VBA, TCSH, BASH, TCL e PERL scripts.● Documented DFT functionalities and guides using XML, directed at internal clients.● Stitched hard block memories into scan chains;● Debugged SA and TD patterns in simulation environment;● Performed IR Drop analysis together with Physical Design team;

Implemented a module in the Moodle environment to enable integration between two databases.● Created import/export backend methods using HTML e PHP, to synchronize mySQL and PostgreSQLdatabases;● Developed a Moodle module to display informations to the end user, using Javascript and HTML;

Developed a prototype for tampering detection using Radio Frequency (RF) mapping through RFID tags.● Configured PIC24F and ATMega16 controllers using C and Assembly;● Defined detection and tracing rules based in infrared, RF and RFID data shared among devices;● Implemented SPI communication protocol between receivers and transceivers in the detection grid,using C.

Scholarship Recipient at Rochester Institute of Technology, sponsored by the Ciências Sem Fronteiras program by CAPES and the Institute of International Education (IIE):● Worked in electronic projects using the Keil tool, C, C++ and Assembly languages;● Designed a feedback control project for a rotor using C;