Prof. Byun received the Ph.D. degree in EE from the UCLA, LA. He is currently Full Professor and Director of the Analog/RF Integrated Circuit and System (ICS) Lab (http://mics.inha.ac.kr) at Inha University in Korea. From 1999 to 2005, he was a Sr. Engineer with Samsung Electronics, where he worked on the design of high-speed DRAMs such as DDR2, GDDR3, Rambus and XDR. In 2006, he was a research intern with Intel where he worked on the design of cache memory and a 3D CMP with RISC core architecture. From 2007 to 2011, he was a Sr. Engineer with Inphi, where he worked on the design of advanced memory buffer, clocking circuit, and high-speed IO circuit design between multi-core CPU and DRAM. His research area includes an Analog/mixed-signal IC design for energy-efficient wireless/wireline communication and RF/THz electronics for sensing/imaging and biomedical applications. He is the author/co-author of over peer-reviewed 70 journal/conference papers and holds 12 US patents in the field of electronic circuits. Dr. Byun was the recipient of the prestigious NSF CAREER Award in 2014 and the NSF BRIGE Award in 2012.[Key publications] - IEEE ISSCC 2012, "An 8Gb/s/pin 4pJ/b/pin Single-T-Line Dual (Base+RF) Band Simultaneous Bidirectional Mobile Memory I/O Interface with Inter-Channel Interference Suppression," Feb. 2012. - IEEE ISSCC 2011, "An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using SBD Dual (Base+RF) band signaling"Specialties: (1) Mixed-signal Electronic & Integrated Circuit(IC) and System Design.(2) High-Performance Analog/Digital IC Devices for High-Speed Wireless/Wire-line Communication.(3) RF/Microwave THz electronics for Sensing/Imaging and Biomedical Applications.(4) Energy-efficient Memory and Multi-core Microprocessor Architecture