郭春炳 Email & Phone Number

Guangzhou, Guangdong Province, Cn

Guangzhou, Guangdong Province, Cn

Guangzhou, China

-ZTE Microelectronics is also called Sanechips-08/2017 ~ present: Leading the development of advanced high speed ADC/DAC development with most advanced FinFet process..-07,2015 ~ 07/2017: Lead the analog mixed-signal team developing Gigabit Ethernet PHY. Manage the design team. Lead and trained team members in their design works. -Developed a competitive Gigabit Ethernet PHY (GE PHY) with SMIC40LL 1.1/3.3V process. This was the most successful mixed signal IP in the company. It was comptetive in both power and area, compared with leading companies in US.-Developed an advanced GEPHY with TSMC28nm 0.9/1.8V process. It was an advanced GEPHY IP with overvoltage circuit design techniques. It enabled Sanechips to compete with leading companies in US.

San Jose, Ca

Lead high speed analog design in 28Gbps SerDes.

Allentown, Pennsylvania Area

Low power and high speed SerDes projects. - Developed AMS mixed mode simulation methodology. Documented step-by-step instructions and trained team members. Everyone in the team was able to use the AMS tool right away with this detailed instruction. It effectively improved the 1st silicon success rate through more thorough verification methodology. - Developed top level dynamic supply noise analysis. Coordinated engineers from various groups, including physical design, analog design, and tool vendors. Debugged and executed flow scripts. Coordinated the review of analysis results, among members from physical design and analog design teams. Figured out the weak path and recommended improvements. Documented detailed instructions and trained team members. - Designed analog CDR circuits including phase interpolator (PI) and dividers. --- Designed a new PI topology of: Thermometer decoder + sinusoidal DAC + mixer. --- Defined non uniform steps in sinusoidal DAC. --- Designed a new structure of 6 bit thermometer decoder with low latency. - Designed PLL circuits including PFD, charge pump, VCO, clock divider. Revised charge pump simulation methodology which improved the accuracy of charge pump model. - Developed a new data slicer by enhancing the sensitivity of a strong arm latch, which achieved sensitivity of a few mV in 65nm 10Gbps SerDes. - Developed the first Power Island scheme for LSI SerDes group. It greatly reduced the leakage current in slumber mode while maintaining a minimum turn-on resistance. - Built and lead a SerDes team (5 engineers) in Shanghai. Trained and motivated the new team to make great achievements. Within less than one year, they could take over complex projects such as migrating a whole SerDes macro from one process to another.

Allentown, Pennsylvania Area

Gigabit Ethernet PHY (1000BASE-T) - Designed a ring OSC based PLL and phase mix circuits - Designed bandgap and bias circuits. Developed glitch free bias line switching techniques. It resolved a problem of causing error bits when turning on/off other lanes. - Designed resistor calibration circuits and algorithm - Designed a 250MSPS SAR ADC. - Designed a 25MHz crystal oscillator.PCI-express - Lead SerDes work in PCIe product.--- Defined serdes specification based on PCIE protocol. E.g. Jitter tolerance, signal amplitude, return loss, sensitivity, etc.--- Selected external IP vendor, based on their performance, power, silicon size, their team strength. Tested their serdes IP in lab.-- - Provided guidance of improvements. Had good reviews with them, pointed out their weakness, suggested improvements. - Built Agere’s PCIe compliance testing lab. Even though not related to circuit design which is my main area of interest, due to lack of resource, I gladly stepped in and took over this work because this was what was needed by the project at that time (since the PCIe PHY was licensed in this product). I purchased instruments, installed test benches, designed automated control software, and executed compliance tests running a battery of hundreds of tests automatically. - Discovered and resolved compliance issues of PCIe SerDes. Debugged the issues and provided effective solutions to the 3rd party SerDes designers. In the end, we were able to pass interoperability tests and get Intel certification. I felt I contributed significantly to the team success by being flexible on my job function (doing almost a year of lab work instead of circuit design), and this was extremely rewarding to me.

Holmdel, New Jersey

QAM transceivers for 40Gbps optical communication - Designed PLL circuits for 13.32GHz clock in QAM-16 transceiver.Backplane linear equalizer - Invented first linear equalizer with both positive zero and negative zero to achieve zero phase distortion while equalizing a 40 inch backplane. It was later widely used in most Agere’s SerDes macros.

Doctor Of Philosophy (Phd), Rfic

Dissertation: A Monolithic 900-MHz CMOS Wireless Transceiver. Involving system design and building block design (Low Noise Amplifier.

Master Of Philosophy (Mphil), Electrical And Electronics Engineering

Bachelor'S Degree, Electrical And Electronics Engineering