Gursimranjit Singh Email & Phone Number

Noida, Uttar Pradesh, India

Working with NEC's Quantum Computing Department to simulate the Quantum-Inspired Annealing Technology on the High Performance Computing (HPC) hardware. This Quantum-Inspired Annealing system aims to improve the solution quality and reduce the computation time of the NP-Hard Combinatorial Optimization Problems, which traditionally have been difficult problems for classical computers to solve.

Irving, Texas, United States

Santa Clara, California

As Senior Systems Engineer, I work on High Performance Computing Technologies, specializing in NEC's PCIe protocol based interconnect solutions. I'm also involved in developing the business strategy and use cases for NEC's next-gen compute products.

Noida Area, India

As Senior Technical Lead, I've lead the development & verification of ExpEther40G system. Presently, I'm working on the verification of 2-slot, 4-slot & 8-slot variants of IO Box in ExpEther40G System.

Noida Area, India

As Technical Lead, my first project was to lead the design & implementation of Image Processing & Enhancement System for NEC Transport Division.The System Development consisted of developing the Image Brightness Enhancement Algorithm using Synthesizable SystemC, implementation of MicroProcessor Control system on FPGA using VHDL/Verilog & development of corresponding FW in C.My Second Project as Technical Lead,40G ExpEther, is an on-going project. I've worked in the role of Technical Advisor in this project. ExpEther is a design which has PCIe Interface at one end & Ethernet Interface at the other. 40G ExpEther enables the connection between two PCIe Devices located at a distance of many kilometers by transmitting PCIe packets over Ethernet.In this project, I've led the activity of understanding the High Level Architecture Specification of the design & creation of Test Scenarios for the verification of the design.

My first project as Module Lead was development of CTB FPGA. CTB FPGA is Communication Tool Box implemented on Altera FPGA. This FPGA is placed between Ethernet PHY & BroadCom Switch. The primary function of CTB is to distribute the load of multiple Ethernet Packets to multiple ports of BroadCom Switch. In case of large sized Ethernet packets, CTB FPGA breaks these packets are into multiple small sized Ethernet Packets & distribute them to multiple ports of BroadCom Switch.Also, CTB receives Ethernet packets from multiple ports of BroadCom Switch & combines them & sends them to Ethernet PHY.I led the development & verification activities of the design & developed various blocks in Verilog.My second project was the conversion of Bird Detect Algorithm in C++ to SystemC. NEC Research Labs created a Software Bird Detection algorithm in C++. This image detection algorithm was used to detect birds on Japan Airport Sights.The Software algorithm was to be converted into Hardware for the purpose of implementing it on FPGA. The C++ Code was converted into Synthesizable SystemC.The Software Algorithm was built using Intel OpenCV APIs. The Intel OpenCV APIs were converted into equivalent SystemC functions.My third project was Design & Verification of an OpenFlow based Switch for NEC Space Division. The Switch is to be placed on Satellite & will communicate with various mobile earth stations using Wireless Modems. I worked on designing the Interfaces of the Switch.

As Member Technical Staff, I designed & implemented Extended Euclidean Algorithm (using 512 bit operands) in INT IP of the CSoC (Cryptographic System on Chip).The design was done in NEC proprietary High Level Synthesis Language "BDL". The validation was done using testcases created using C Language.I also designed & implemented Division operator in Cryptographic SoC using NEC proprietary BDL High Level Design Language. The Division operator was implemented in such a way that it provided support against Timing Side Channel Attacks. Every computation done by Division operator is performed in constant time.In addition, I developed Single Precision Floating Point Square Root & Exponentiation IP using Verilog HDL.

As Software Engineer Trainee, I undertook product validation of Spyglass Tool's kernel Layer. The tasks included understanding of new features incorporated in the Spyglass kernel in every release & validation of those features by creating test scenarios. The test scenarios were created in HDL languages( Verilog,VHDL) & Programming Languages(C/C++).

Post Graduate Diploma, Embedded Systems & Vlsi Design

B.Tech., Electronics & Communication Engineering

Activities and Societies: 6 Month's internship at IIT Delhi on the subject of Photovoltaics Technology 2 Month's training at IIT Kharagpur.