Hitesh Ahuja Email & Phone Number

Pittsburgh, PA, US

Pittsburgh, Pennsylvania, United States

• Researching low-power neuro-morphic camera design on FPGA/ASIC with partially asynchronous read-out implemented in RTL for 1MP frames at > 6000 fps.
• Converted HDL code to gate-level netlist and verified design functionality through simulation.Generated physical layout using Innovus including automatic placement, and routing, and verified it in Cadence virtuoso.
• Researched various architectures for feature extraction from pixel events and image reconstruction using only 6 events, utilizing the chosen architecture to send data to a spiking neural network for pattern recognition.
• Developed Python code for noise cancellation using image processing techniques to reduce qDVS camera noise by 60%.
• Designing process in-memory computation capable race track memory simulator (RTSim based on NVMain) in C++ and created test benches in Cadence virtuoso to report 40% leakage component in the novel memory.
• Co-lead development of cycle-accurate Tomasulo Algorithm in Python with support for speculative execution, successfully passed over 20 complex benchmark programs for both Integer and FP-32 instructions.

Bengaluru, Karnataka, India

Worked in a project to develop a functionality for Geo-Location Intelligence Service in the presentmodel of the app using Java Spring Boot. Worked with databases, APIs etc. using Spring Framework.

Noida, Uttar Pradesh, India

• Designed high-speed analog and digital circuit components using Cadence Virtuoso in 5nm and 16nm technology, including layout, schematics, and test benches.
• Taped out a 16nm BTTC thermometer decoder and designed a power-on-reset block layout in 5nm for novel Phase Locked Loops (PLLs).

Noida, Uttar Pradesh, India

Pilani, India

• Researched hardware-software co-design to reduce area requirements of deep neural networks on Jetson TX2 embedded board, achieved 96% detection accuracy for driver drowsiness, and published in IEEE INDICON 2020.
• Developed block-chain-based simulation framework for 5G applications, including infrastructure sharing and network slicing details using Java.
• Designed SPICE macromodel and read circuit for ISFET device, compensated for temperature and temporal drift components by 60x using machine learning models like random forest.Led to publications in IEEE Transactions on.

Chennai Area, India

• Eased the process of leather certification by segmentation of leather pores using image processingtechniques like Otsu’s segmentation, Morphological operations in MATLAB
• Prepared the dataset for the image classification of leather samples based on the pores and achieved 89.4% accuracy on the pore identification from the leather samples.

Doctor Of Philosophy - Phd, Electrical And Computer Engineering, 3.893/4

Master Of Engineering - Meng, Microelectronics, 9.05/10

Bachelor Of Engineering - Be (Hons.), Electronics & Instrumentation Engineering, 7.42/10

Activities and Societies: National Service Scheme (NSS) BITS Pilani, MadhyanshI have served as leaders in both the organizations that I.