Haim Rodal Email & Phone Number

Israel

Israel

Judea And Samaria Area, Israel

Electronics & Software tutor, lecturer & mentor @ courses like C,C++ programming, Digital Systems, VHDL design, Matlab, Networks, and Micro-Processors. I also established FPGA Altera Lab and electricity lab for practical engineers. I am a lecturing & tutoring at: --> Bar Ilan University. --> Ariel University Center of Samaria. --> Ruppin Academic Center..

Tel Aviv District, Israel

• UVM system Verilog FPGA verification.
• Developing verification base classes and infrastructures.
• Developing Internal bus protocols verification.
• Registers automation verification.

Airport CITY, Israel

• UVM system Verilog FPGA verification.
• 4G/5G LPR and HDDOM verification.
• Protocols– CPRI, AMBA. Tools: Python, RAL, SoConline.
• Corning verification inner-technologies development.

Netanya

• UVM system Verilog ASIC verification.
• Verification coding using e (Specman), eVC’s and eRM.Projects: Intel CovePeak project - ASIC for digital image processing. I was responsible for the CSI-MIPI2 cluster verification (both TX & RX) including CSI-MIPI2.

Jerusalem

• Technical leading of 5 verification engineer part of the ACT-logic group.
• KRM-PHY project - common cluster verification both for BDX and DNV.
• Developing digital section verification environment – RAL & registers, Common, Init-FSM
• Developing MSV environment including analog IF and calibrations.

• Star-Core DSP project using SV & VMM.
• Core-pipe verification developing the new TB for LSI DSP core:--> Developing Core-Pipe stage monitor.--> Developing support for multi-thread & stages growth.
• Developing the new ESQ2SIM module as interface to the LSI inner-simulator.
• Verifying memory segmentation.

• Multi language environment - combining System-Verilog language together with e (Specman) language in Cadence simulation tool.

• Responsible for XML block verification at Prism processor.
• Developing Verification environment using Fusion tool & C++.
• Assimilating DataPower verification using C and C++.
• Supporting Fusion CAD team.

• Responsible for all ECC memory tests, Interrupts tests, Multi and first.
• Developing new verification components in System Verilog.
• Migrating part of the verification environment from Vera-NTB to System Verilog.

• VIER block verification - environment architecture up to final tests.
• VIER Regressions and Coverage.
• Developing using Specman (e)

QA & Verification Team Leader for almost 3 years. Develop in-housesolutions for testing the R-1 – state of the art replication tool. The working environment includes Perl, C and C++, documentations and tests results analysis.as a team leader I assimilated Perl and automation @Repliweb!

ASIC Verification consultant Engineer (freelancer) - responsible for IP8052 MCU testing and instantiation. Design C and Assembler tests, VHDL verification and digital part programming into NIOS [Stratix-II FPGA] board.

ASIC Verification Engineer at KereniX Ltd – Design and verification role in control path project. Tests definitions, building and execution under Verilog and Specman like environment [based on C++]. I Worked with SERDES, 8B10B and VCS tool.

Master Of Science (M.Sc.), Electro-Optics, Cam-Laude

[Graduated with Honors - merit]

M.B.A, Business Administration

currently studies are at hold due to a long vacation.

B.Sc, Cse - Communication System Engineering