Principal Consultant
Current
May 2015 - Present
AeroLeads people directory · profile
Hamilton Carter Email & Phone Number
Principal Verification Consultant
at
Mentor Graphics
1 work email found
@mentor.com
3 phones found area 415 and 503
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Current company
Role
Principal Verification Consultant
Location
San Francisco, California, United States
Who is Hamilton Carter? Overview
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Quick answer
Hamilton Carter is listed as Principal Verification Consultant at Mentor Graphics, based in San Francisco, California, United States. AeroLeads shows a work email signal at mentor.com, phone signal with area code 415, 503, and a matched LinkedIn profile for Hamilton Carter.
Hamilton Carter previously worked as Principal Consultant at Mentor Graphics and Senior Editor at Jb Systems. Hamilton Carter studied at The Ohio State University.
Company email context
Email format at Mentor Graphics
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{first}_{last}@mentor.com
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AeroLeads found 1 current-domain work email signal for Hamilton Carter. Compare company email patterns before reaching out.
Profile bio
About Hamilton Carter
Author of Metric Driven Verification. Verification evangelist who enjoys improving SoC verification processes from the top down and who has architected and built verification systems from the bottom up.
Listed skills include Functional Verification, Soc, Eda, Asic, and 31 others.
Current workplace
Hamilton Carter's current company
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13 roles · 32 years
Hamilton Carter work experience
A career timeline built from the work history available for this profile.
Senior Editor
Current
Jb Systems
Oct 2014 - Present
Senior Eda Editor/Low-Power Engineering
Current
Extensionmedia
Jun 2011 - Present
Research Assistant
Aug 2012 - Jun 2015
Chief Design Verification Consultant
Pythagorean Productions
Consulted with various companies building metric driven verification plans and eRM/UVM compliant environments.
Jan 2008 - May 2015
Verification Engeineer
Verified various blocks within the hard disk controller. Worked with USB, I2C, and interrupts as well as queuing blocks. Trained engineers in metric/coverage driven verification methodologies and eRM.
2010 - 2011
~1 yr
Verification Consultant
Implemented block level eRM verification modules in Specman for various blocks of a hard drive controller.
2009 - 2010
~1 yr
Core Competency Architect
Coordinated engineering teams and managed strategies for customer deployments, key contributor to closing global sales; presented engineering sales training at domestic and international sites, presented methodology at seminars, conventions, and customer sites, trained AEs in engagement techniques and served as point of contact during engagementsI helped.
2005 - 2007
~2 yrs
Senior Consulting Engineer
Worked with customers to architect and implement their Specman enabled verification environments. Presented seminars, and trainings related to Specman and the e Reuse Methodology (eRM). I consulted at several companies including, Intel, IBM, Toshiba, STMicroelectronics, Texas Instruments, and Freescale. Worked with sales to qualify new opportunities within.
2003 - 2005
~2 yrs
Senior Verification Engineer
Layern Networks
Built verification environments specific to SSL and TLS secure handshakes and cryptography algorithms such as AES and RSA. Worked with ARC processors as well as custom crypto and TCP network stack IP.
2001 - 2003
~2 yrs
Soc Verification Product Director
Developed architectures, implemented prototypes, and made initial sales calls for three verification tools: a random stimulus generator, an object-oriented modeling and checking framework ala eRM/UVM precursor methodologies, and a functional coverage collection and analysis engine.
2000 - 2001
~1 yr
Verification Manager
Started and managed Cirrus' first verification team. Responsible for hiring, negotiations, and management. Architected and managed implementation of Cirrus' object-oriented verification environment. Worked with design and business management to set schedules and goals for successful verification of mixed-signal MP3 audio devices utilizing ARM processors..
1998 - 2000
~2 yrs
Senior Verification Engineer
Architected, implemented, and deployed an object oriented verification checking system that was a contemporary of eRM and a precursor to VMM/OVM/UVM. The architecture allowed for and encouraged orthogonal bus monitors, including functional coverage and DUT models. Configuration register stimulus and monitoring code was automatically generated by an SQL.
1994 - 1998
~4 yrs
5 education records
Hamilton Carter education
Education record
The Ohio State University
Education record
New Mexico State University
Education record
New Mexico State University
Education record
Ruidoso High School
Education record
Texas A&M University
FAQ
Frequently asked questions about Hamilton Carter
Quick answers generated from the profile data available on this page.
What company does Hamilton Carter work for?
Hamilton Carter works for Mentor Graphics.
What is Hamilton Carter's role at Mentor Graphics?
Hamilton Carter is listed as Principal Verification Consultant at Mentor Graphics.
What is Hamilton Carter's email address?
AeroLeads has found 1 work email signal at @mentor.com for Hamilton Carter at Mentor Graphics.
What is Hamilton Carter's phone number?
AeroLeads has found 3 phone signal(s) with area code 415, 503 for Hamilton Carter at Mentor Graphics.
Where is Hamilton Carter based?
Hamilton Carter is based in San Francisco, California, United States while working with Mentor Graphics.
What companies has Hamilton Carter worked for?
Hamilton Carter has worked for Mentor Graphics, Jb Systems, Extensionmedia, Texas A&M University, and Pythagorean Productions.
How can I contact Hamilton Carter?
You can use AeroLeads to view verified contact signals for Hamilton Carter at Mentor Graphics, including work email, phone, and LinkedIn data when available.
What schools did Hamilton Carter attend?
Hamilton Carter studied at The Ohio State University.
What skills is Hamilton Carter known for?
Hamilton Carter is listed with skills including Functional Verification, Soc, Eda, Asic, Systemverilog, Semiconductors, Debugging, and Verilog.
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