Cheng Han Hsieh Email & Phone Number

Hsinchu, Tiawan

1. OpenCL framework project• Developed an OpenCL runtime for a cluster of RISC-V cores.• Utilized open-source projects such as PoCL and llvm-project as the foundation.• Customer desgin service: integrated DMA in the OpenCL API.• Verified using OpenCL CTS (Conformance Test Suite) and resolved customer issues.2. Edge AI RISC-V Vector Accelerator (RISC-V CPU + RVV VPU)• Brought up the latest heterogeneous platform, managing Linux boot flow and U-Boot.• Ported OpenAMP as an RPC solution between the host and the RISC-V vector accelerator.• Integrated the RPC solution into TensorFlow Lite model delegates, offloading the Neural NetworkLibrary to the accelerator for computing efficiency.3. Acceleration Libraries• Ported high level NN library to RISC-V platform, including ACL (Arm Compute Library), TFLite withXNNPACK and ONNXruntime.4. Baremetal acceleration• Accelearate bare-metal Mobilenet-v1 program by DMA and multi-bank memory.