Company: Sasken Communications Technologies Limited Duration: April 2002 to Feb-2011. (in various roles such as Sr,. Verification Engineer, module lead, Tech Lead and then as a Project Manager)Managed IP and SoC functional verification for cross-functional teams. Participated with architecture, design, software, and more teams to define the overall verification strategy of IPs, Sub systems and SoCs. Managed engineering teams.1. Project: Leading Specman and C-HDL based IP and SOC Verification teams as a Verification Project Manager. The IP’s ranging from low complexity levels to high complexity level in terms of functionality and gate count, having individual IP tailored specman Verification environments, test data base and functional grids. Role: Project ManagerTeam Size: 20 members. Responsibility: a. Rampup team in specman based verification methodology. Managing around 10 IPs and four subsystem and one SOC verification activities b. Verification plan development, Schedules, reviews, risk management and Release Management.c. Planning, scheduling, Technical support and tracking of the verification activityd. PM, Delivery management and Milestone reviews with customers for signoff against the agreed quality metrics.Project Duration: Starting from Feb 2007 to Feb 2010.2. Context IP Messaging IP verification(HVL: Specman):Verification Plan Development, Environment development and verification.3. Project: System Level Verification OMAP3430 Role: Lead (Verification).Responsibility: Individual contributor in Memory subsystem (hard macro) and Front end point of contact to the customer for top level verification team. My job involved testing of memory subsystem using the standard verification environment. The required scenarios were developed using ‘c’ language. Duration: Feb 2006 to Feb 2007.4. Project: Verification of SDRC (SDRAM Controller) using Specman. Duration: Nov 2003 to Jan 2005.The Project executed from TI-Dallas.

Project and Job Responsibility:1) Involved in the implementation of Traffic Control Units of High speed Programmable communication Processor which is System on a Chip(SOC).Link Interface TCU controls the bi-directional data transfer based on Utopia level 2, Version 1.0, and POS (Packet Over SONET) protocol L-2. It has 800 Mbps throughput and supports multiple physical devices with all three standard Utopia selection mechanisms. The pending requests from physical interface can be prioritized with fixed priority or round robin priority schemes. The interface also maps flow tag identifiers from packet header into the local channel number used for accessing flow state information.Traffic Control units are responsible for pre fetching traffic data and flow program information for the particular packet event before moving it into Packet Processor registers files. TCU's are also responsible to receive cells/packets from Packet Processor or some other TCU to transfer the same to specified PHY port.Implemented the logic to support continuous traffic by revolving buffers.Languages and tools used:VHDL, Vsystem VHDL Simulator, Synopsys Synthesis tools, Code Coverage tools from TransEDA and HDL co-simulation tool from Synopsys.Knowledge Gained:UTOPIA level-1 and level-2, POS-PHY Interface L2. Design of high speed digital logic. Dedicated and shared bus functional models. System Bus Architecture, Code Coverage techniques,

verification Engineer - worked on IMA (Inverse Multiplexing over ATM)