Hao Li Email and Phone Number

Lead sensors development for autonomous delivery vehicles, building and managing multi-discipline teams (LiDAR, Radar, Camera, FPGA firmware, Sensor Validation, Integration, and Testing, etc.)

Lead LiDAR and FPGA firmware development

Lead optical sensors development for autonomous vehicles

Developing advanced transmitter techniques for 4G LTE handset modem, including digital predistortion for baseband/RF nonlinear amplifier, I/Q imbalance correction, envelope tracking, close loop PA output power control, adaptive antenna tuning, etc.Evaluating envelope tracking (ET) switchers for RF PA from various vendors, and developing ET path delay estimation and compensation algorithm.

• Developed high data rate RF telemetry scheme for implantable brain neural sensor device, an OOK/BPSK receiver with off-the-shelf components, and an customized integrated wireless transmitter in 0.18um BiCMOS to achieve 100Mbps data rate and 0.1nJ/bit power efficiency, in progress• Designed analog sub-channel separation circuits (channelizer) for independent component analysis (ICA) in a ultra-wide band cognitive radio receiver, in progress

• Developed wideband adaptive DPD algorithm for base station RF power amplifiers for multi-standard radio. • Implemented LMS-based DPD algorithm on Xilinx FPGA with Verilog for prototype verification, including DPD, DUC/DDC, TX/RX channel equalization LMS engine, time aligning, etc., and supported ASIC design/verification. • Investigated new approaches for GaN power amplifier nonlinear behavior modeling, ultra-wideband multi-carrier DPD (60 MHz up to 100 MHz), and non-continuous band DPD (dual-band and carrier aggregation in LTE)• Analyzed state-of-art DFE solutions from various providers, including TI, Xilinx, Altera, Optichron/Netlogic, Scientera, etc.

Digital predistortion technique for RF power amplifier linearization• Developed a novel LUT-based digital predistortion (DPD) algorithm with fast adaptation and a hardware-efficient loop delay compensation scheme for integrated CMOS RF PAs in 0.13um process• Implemented DPD system on FPGA with VHDL for prototype verification and integrated PA testing• Improved the measured transmitter EVM from 9.1% to 3.3% by DPD, with 12.5% PAE and 13.2dBm output power for a 20-MHz 64-QAM OFDM signal at 3.5GHz carrier frequencyAdaptive digital background calibration for pipelined ADC• Developed an adaptive background ADC calibration algorithm for high-resolution pipelined ADC, based on sample prediction and equalization• Led a team to design a digitally calibrated pipelined ADC prototype in 65nm CMOS process, served as the system-level architecture and calibration algorithm designer• Performed chip debugging and testing work• Achieved 67dB peak SNDR and 84dB peak SFDR at 150MHz sampling rate when enabling calibration, with only 48mW power consumption from 1.2V supply and a FOM of 194fJ/conversion-step. Phase-oversampling vector modulator for MIMO receiver• Explored the new MIMO receiver architecture based on phase-oversampling vector modulator with another Ph.D. student, and built the behavior simulation model for verification. • Helped testing the vector modulator prototype in 90nm CMOS process.

• Developed behavior model for a low-IF DECT receiver, and built SIMULINK/Verilog-A model for system planning and performance verification• Designed a passive down-conversion mixer, including LO generator, passive mixer and trans-impedance amplifier for low-IF DECT receiver in 0.13um CMOS process

• Led a team to design a high-accuracy transient waveform digitizer targeting 1GSPS sampling rate and 250MHz input bandwidth, and designed a switched capacitor array based front-end sampler in 0.35 CMOS process at schematic level, including input buffer, switched capacitor array, DLL multi-phase clock, and pre-amplifier.• developed the FPGA-based time-to-digital converter (TDC) utilizing dedicated carry-chain for time interpolation, and implemented a prototype in Xilinx Spartan FPGA, achieving 50 picoseconds time resolution