Senior Machine Learning Engineer
CurrentCollaborated with VLSI and Package teams to integrate machine learning techniques into chip design automation tools, improving efficiency and automation.- Developed a deep learning model using Transformers to accelerate eye diagram analysis for high-speed links, improving efficiency and enhancing simulation processes.- Directed a team to create a Transformer-based power grid optimization tool, optimizing voltage drop minimization across different process nodes.- Led the development of a graph-based Transformer model for IR drop prediction in early-stage SoC designs, supporting advanced CoWoS packaging and enabling a shift-left approach.