Hari K Rajeev Email & Phone Number

George Town, Penang, My

Penang, Malaysia

DFx/Diagnosis Engineer

Penang, Malaysia

-Manufacturing DFx Technical readiness lead for Low End FPGA designs going into the AGILEX3 Series products. -Scan Lead for all Intel FPGA products, responsible for Silicon bring up of the ATPG content, Yield improvement , test time reduction.

Penang, Malaysia

Scan Engineer for FPGA chips in the Intel PSG division. - Responsible for development, generation and silicon bring-up of transceiver IP content across 22nm and 16nm nodes. - Worked on developing and bringing up Memory IP ATPG content in the FPGA Core logic for the 14nm product. - Drove Test coverage, test time and yield improvement activities on 20nm,14nm & 10nm FPGA products. - Exploring feasibility to do Cell-Aware ATPG and test methodology improvements for Custom FPGA IPs in the 10nm product line.

- Developed Hierarchical Test Methodology for the entire IBM Processor Group.- Worked on developing Hierarchical Test Architecture for new high-end IBM Processor Chip (14nm).- Responsible for Scan Compression architecture and pattern generation for new high-end IBM Processor Chip (14nm).

- Instrumental in the migration of the Scan insertion methodology work to Bangalore and setting up a team to continue this work remotely.- Lead the development of an internal LBIST Methodology for OEM ASICs. • Prototyped the generic LBIST Methodology for OEM ASICs • Developed the LBIST insertion Methodology • Driving the LBIST Encounter Test based Scan Verification and Pattern Generation Flow development. • LBIST Execution lead for LBIST insertion, Verification (DRC Checks) and Signature Generation on 2 Large ASIC designs.- Worked on creating BSDL and verifying it against couple of Large Server Designs that were largely 1149-uncompliant.- Nominated to be part of the Talent Sparks community in IBM which is a focus group of high performers.- Developed LBIST Scan patterns and ATPG on Large high-end IBM Processor Chip (22nm)

- Drove the effort to architect and develop Scan Insertion Methodology for ASICs in 32nm.- Worked on and made design changes to 2 large Server ASICs to make it 1149-compliant.- Worked on Mentor Graphics (MG) Test Tool Evaluation for OEM ASICs. • Responsible for the evaluation of Scan Insertion, TestKompress insertion and Scan Verification (DRC Checks) and Scan Pattern Generation • Worked with the MG AEs in India and US to create the spec for the utilities and gap analysis.- Imparted ASIC DFT methodology training to many customers, internal designers and new hires.- Received “The Best of IBM! - Eminence and Excellence Award” for outstanding contributions to Systems and Technology group.

- Responsible for creating and implementing a test and scan insertion methodology that was used to do scan insertion and test insertion for more than a 100 ASICs- Responsible for the development/maintenance/support of DFT insertion Methodologies in 90nm, 65nm and 45nm. - Drove the effort to develop Out-of-context DFT insertion methodology for ASICs.- Worked in a cross-organization project that studied test compression that we used and based on experimental data on many ASICs, made suggestions to the worldwide design center on optimal fan-out factors

B-Tech, Electronics

Bachelor'S In Technology, Electrical, Electronics And Communications Engineering

Pre-Degree, Science

High School