Global leader for R&D for WCS with teams in Bangalore, San Jose and Singapore for USB Type C/PD, Charger/Adapter and wireless charging products.

I am heading the design center for Wired Connectivity solution focusing on USB Type C/PD products including AC-DC, DC-DC and wireless charging

WiFi/BT/BLE Combo Program in 40nm (CYW4373)* Leading the wireless combo chip that combines 802.11ac high-performance Wi-Fi, Bluetooth and Bluetooth Low Energy for IoT applications* Responsible for all aspects of engineering including silicon, FW, SW, Application notes, Development kits, and Reference design kitsBluetooth Low Energy Program in 130/55nm (PSoC4A-BLE-II)* Led second generation BLE chip with 3X better RF current and 2X better system power in 130nm PSoC and 55nm Radio as SiP* Responsible for all aspects of product delivery including silicon, FW, SW, Application notes, Development kits, Reference design kits and marketing collateralBluetooth Low Energy Program in 130nm (PSoC4A-BLE)* Started Bluetooth Low energy group and managed first program in India with 150+ engineers across 9 global sites as Strategic Product Leader* Responsible for all aspects of product delivery including silicon, FW, SW, Application notes, Development kits, Reference design kits and marketing collateral* First ever Cypress product to integrate Radio, PSoC and Capsense on a single die* Successfully delivered first time working silicon and achieved Public launch at Electronica 2014 in Germany

* Relocated to India to start the DCD-India design center* Carved out design center with 20 engineers in India and managed all aspects of the design center including P&L

USB-Serial Program in 130nm (USB2.0FS to Serial interface bridge)* Technical leader for 40+ design engineers across 3 global design centers * Involved in full tern key model for backend and logic verification using contractors* Delivered fully working silicon for USB2.0FS to serial interfaces (UART, SPI, I2C)* Supervised all technical efforts for the Chip including USB IP design, Logic Verification, Mixed Signal Verification, Floorplan, and Chip integration* Worked with Mkt/Apps, Arch, FW, Design and Verification teams to deliver the productPoint of Load DC-DC converter chip (Power Management IC for POL Applications)* Worked with Architecture team to define a highly programmable SMPS Controller with Configurable Power Stages and flexible System Management Controller* Worked with technology group to define 24V process for next generation PMICUSB3.0 Controller Chip* Worked on full-chip ISB verification and defined a new methodology for complex chip with 2M gates and 25 circuit/analog IP blocks. The methodology was adopted across other products in the CompanyPower PSoC Chip for LED Driver (Power Management IC for LED Driver)* Technical leader for 30+ design engineers across 5 global sites for first Power PSoC chip* Delivered first time working silicon for 36V/1A/4ch/2MHz hysteretic controller LED driver part.* Designed unique reconfigurable power electronic controller IP. Devised major design concepts and led team to design integrated IP blocks such as power MOSFETs, Hysteretic Controllers, Peak Current Mode Switching regulator, High Side Current Sense Amplifiers, DACs, Microcontroller, and Flash Memory* Worked closely with Marketing and Applications group in defining the part Architecture for LED Driver and topologies* Defined chip floorplan and power bussing for optimal area, power and noise isolation from High Voltage FETs

TurboCAM (High volume 4.5Mb Ternary CAM ASIC for Cisco Systems)* Technical leader for 30+ design engineers across 4 global design centers* Produced first time working silicon conforming to all datasheet specifications* Defined highly constrained timing budgets and modes for 8 products integrated into one die* Authored CAM Core micro architecture spec and defined full chip clock tree architecture* Defined a high dynamic current (30A/ns) regulator to achieve backward compatibilityTCAM4 (High performance 20Mb ASIC for Cisco Systems)* Technical leader for 20+ engineers globally for CAM core, high-speed IO, PLL and clock tree* Conceived, proposed and co-developed with Cisco a new 1.2V, 1Gbps source synchronous parallel interface specification. This was later adapted for JEDEC 1.2V BIC standard.* Designed read SA and new pseudo-differential MSA to operate at 1.0V, 250MHz

* Designed a PFD and Charge Pump in BiCMOS SiGe technology for OC192 SERDES Chip* Design/layout of 2.5V CML standard Cell library* Design/layout of Phase Frequency Detector* Design of 2.4GHz CML Output Driver * Design of Serializer in SiGe technology

* Designed an output driver (PECL/DDR/SSTL2/SSTL3), folded Cascade OPAMP, and open drain output driver for Clock synthesizer chip to be used in Intel Chipset* Designed/Developed three clock synthesizer projects including zero delay buffer

* Worked on two asynchronous SRAM projects* Designed low power 64Kx16 SRAM and fast 128Kx16 SRAM