Hi connections I am Harish, 2021 engineering graduate. Completed my training in VLSI domain and I've a 10 month working experience as a design and Verification Engineer. >> Skills - Verilog, System Verilog, UVM,STA>> Area of interest - ASIC Verification, SOC Verification, RTL Design, Semiconductor >>VLSI Design and Verification Engineer, has a interest to learn and to innovate new ideas . Equally open to working and sharing responsibilities with a team . Possess capabilities of working with a team and alone . Able to work hard and likes smart work.>>To work smart with full determination and dedication to achieve organizational as well as personal goals.