Design Verification Engineer
CurrentPCIe Gen5 and Gen6 Physical Layer VerificationSkills Coding Languages: Verilog, System Verilog Methodologies: UVM and OVM Verification/Design Tools: Synopsys VCS & Verdi Protocols: PCIe Gen5 and Gen6 Physical Layer, CXL.io Documentation/Presentation Tool: Vim, Microsoft PowerPoint, Excel, Word Cross cultural communication