As an individual contributor, my primary objective is efficient hardware implementation by performing path-finding and design-space exploration (DSE). My collaboration with key stakeholders, including RTL designers, firmware teams, architects, and physical design teams, results in innovative solutions and efficient integration processes. My expertise in Silicon Hive (DSP) technology, Network on Chip (NOC), and external IP integration, such as Cadence Tensilica (Xtensa) DSPs, drives the advancement of our hardware capabilities. The activities include:- Characterize and optimize Performance, Power, and Area (PPA) Key Performance Indicators (KPIs) by running EDA tools such as Fusion Compiler, RTL-architect, and PrimePower, early in the design cycle or upon the addition of new features.- Customize and/or restructure the logic designs (RTL) to prepare for layout partitions, aiming to achieve silicon-efficient partitions that ensure optimal EDA flow runtimes and minimal inter-partition connections. This is enabled by deploying advanced RTL methodologies using tools like Defacto and Synopsys GenSys/RTL-architect.- Serve as a bridge between Silicon Hive-based DSP methodology and the integration and implementation teams, resolving timing path violations and coaching physical designers on synthesis and floorplan guidelines to enhance design efficiency and performance. Also supporting RTL quality activities like Linting (e.g. (VC) Spyglass). When needed cooperated with the (internal) customer on-site.- Conduct DSE on third-party IP to benchmark and understand the competitive landscape, providing insights that inform strategic decisions and drive technological advancements.- Optimized the RTL generation tool for more efficient resource mapping onto Altera Agilex family FPGA resources, including block RAMs, LUTs, and register files, utilizing Quartus II software.

- Build from scratch and managed a team of Physical Designers (team size 10). Through my leadership the team did the implementation of complex imaging IP layout partitions by using both industry standard EDA tools, but using some proprietary tools as well. The work involved the whole spectrum of Physical Design: like logic synthesis, constraint review, P&R , static timing analysis, power integrity validation and quality checks. Daily activities involved people and career management, student coaching, interface with EDA vendors and interface with Design Automation (DA) groups. - Physical implementation project management, was responsible for all aspects of project execution, including layout-partition implementation and layout-partition integration; ensuring product specifications are met by KPI optimization, project planning, managing escalations, stakeholder management (RTL, flow, library, architecture, vendors). All this in close cooperation with Intel sites across different locations (Israel, US, India). - Next to managerial responsibilities, as individual contributor worked closely with logic design and architecture disciplines to ensure future imaging IP generations meets PPA (area, timing and power) targets; for both internal and third-party IP. These path finding activities had a strong focus to reduce road blocks for smooth physical implementation and integration.

Being part of this exciting start-up from the beginning. This start-up span-out from Philips Research and supplies Semiconductor Intellectual properties (IP). It designs, builds, and licenses application-specific system solutions for use in consumer electronics and mobile terminals applications by semiconductor manufacturers and original equipment manufacturers (OEM). Silicon Hive was acquired by Intel in 2011.Performed various roles:- Front-end design (RTL) coding for parts of ASIPs instruction-set- Project management of imaging& Video demos of our IPs: hardware design, firmware development and FPGA mapping and validation.- Characterization of HW IP blocks in terms of area/timing and power and make sure the HW IP has smooth SD/backend integration with EDA tools (Cadence and Synopsys synthesis and Place&Route tools). Work closely with frontend and architecture teams to ensure IPs meets area/timing and power targets.- Provided feedback to RTL generation tool development on RTL customization needs based on customer feedback.- Team leader of small team responsible for RTL deliveries to customers, verification and characterization of soft-IP (RTL) deliveries. Responsible for smooth HW/backend integration at customers, by doing (on-site) support. Used feedback from customers to improve the IP.

Various roles:- Diagnostics/failure analysis on Integrated circuits (Light Emission Microscopy, liquid crystal, Pico probing) (~3.5 years). As laboratory assistant providing diagnostic services to design teams and help design teams to pinpoint design failures. Furthermore, as research assistant contributed to some internal reports on application of light-emission microscopy and on spectral analysis in light emission microscopy.- Worked on Signal Integrity and EMC SOC design rules as part of multidisciplinary EMC taskforce (~4 years). As part of this work we designed a test IC with various design structures to verify our claims (e.g. ring oscillators, different types of decoupling capacitors, various power grid structures). I did full Structural Design for this IC.- Member of team delivering IC design services for Research teams. Switched to frontend (RTL) and micro architectural design work. Worked with behavioral synthesis tools (e.g. ART designer) for creating Application Specific Instruction-Set (ASIP) processors. Did frontend design (RTL) coding for parts of instruction set. Contributed to several internal reports on audio/video and graphics ASIPs.