Harry Luan Email and Phone Number
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An innovative, energetic, and results-oriented leader experienced in semiconductor R&D management, process integration, device engineering, product development, reliability qualification and yield enhancement. Excels in both engineering management and individual contributor roles.- An experienced manager having strong skills in team building, problem solving, people motivation, and on-time/within-budget project delivery.- Strong background in leading-edge semiconductor process technologies, integration, device physics & engineering, product reliability, product qualification, and technology roadmaping. - Extensive working experience in all aspect of semiconductor memory development from inception to production, including device design, process architecture, module integration, design rule development and check, device physics and modeling, test chip design and layout/tapeout, yield enhancement and management, and product reliability and qualification.- Multi-disciplinary knowledge/experience allows handling technical challenges with strong end results.- Hands-on familiarity with TCAD and IC EDA tools, bench device characterization instruments, and PFA techniques.
Nantero, Inc.
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Vp, Integration And Device EngineeringNantero, Inc. Aug 2018 - PresentWoburn, Massachusetts, UsResponsible for process integration and device engineering of Nantero's CNT-based NRAM memory technology. Managing memory cell modeling (physical and compact), technology scaling, yield improvement and failure analysis, technology and product reliability.
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Chief Technology OfficerTc Lab, Inc. Jan 2018 - Aug 2018Improved existing and developed new 3D thyristor cell structures for performance, reliability, manufacturability, and low cost. Developed technology roadmap beyond 64 layers; Benchmarked against existing and emerging technologies. Completed TCAD verification of cell design, operation, and array disturb margins under process variability. Worked closely with potential customers, wafer fabrication vendors and VCs.
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Cto, Sr. Vp Of R&DKilopass Technology, Inc Feb 2009 - Jan 2018Mountain View, California, UsDeveloped new volatile DRAM & SRAM cell technologies, which were successfully spined off. Invented and enabled productization of new technologies for antifuse memories down to 10nm. Responsible for all new product innovations, development, and qualification. Managed the company engineering including all functional departments for improved product delivery. Responsible for technology development, product reliability, and worldwide Foundry operations.Led major IP customer acquisitions and Technology licensing to DRAM manufactures and Foundries. Oversaw intellectual property development and protections Developed technology roadmap and helped the strategic focus of the corporation Performed due diligence on emerging technologies, competitors, and acquisition targets -
Director Of Technology DevelopmentKilopass Technology, Inc. Jan 2005 - Feb 2009Managed memory technology development and worldwide Foundry operations. Responsible for new memory cell innovation, architecture and scaling. Established IP partnership with major CMOS foundries, including TSMC, UMC, SMIC, etc. Completed OTP memory IP qualifications at major Foundries from 180nm to 55nm. Built the first physics-based Spice models for Kilopass’ antifuse memory cell. Supported key customers at both pre-sale and post-sale stages. Oversaw intellectual property development and protection.
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Manager Of Technology DevelopmentWinbond Electronics Corporation America Feb 2003 - Jan 2005Managed the research and development of future generation NVM technologies, including floating gate, charge trapping, and resistive switching RAMs. Achieved significant progress in a memory device based on resistance switching by working with various academic research groups. Designed an 8Mb dual-bit MONOS test chip and obtained working 1st Si on 0.11um process. Extensive device characterization resulted in the understanding of endurance and charge retention mechanisms. Provided specifications to design and module groups to achieve competitive performance and reliability. Significantly improved the device reliability through operation and process optimization. -
Director Of Technology DevelopmentKilopass Technology, Inc. Aug 2002 - Feb 2003Built the device lab, established design flow, and implemented a quality management system at the startup. Responsible for the development of a new CMOS compatible non-volatile memory. Successfully verified the device design, product implementation, and reliability across multiple foundries. Oversaw foundry operations, product qualification, and design support.
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Sr. Principal EngineerCypress Semiconductor Mar 2001 - Aug 2002San Jose, Ca, UsResponsible for technology development and design support of CPLD, CAMs, and other comm. products on TSMC’s 0.13um process. Evaluated different foundry technologies based on product requirement. Led a cross-functional team improving 0.18um CPLD yield from 63% to 91%. In charge of TSMC’s 0.18um platform technology support, including EDR, TDR, SPICE models, and product tapeout. -
Sr. Principal EngineerHynix Semiconductor Mar 1996 - Feb 2001Icheon, Gyeonggi-Do, KrCompleted 0.13um Flash cell and array architecture and process flow. Developed 0.25um Flash EPROM technology and transferred to manufacturing. Responsible for process integration of Hyundai’s 1st 0.35um stacked gate Flash EPROM. Defined process flow, generated design rules, and designed test chips. Achieved excellent 1MB test chip result on the 1st Si. Developed Flash specific modules such as Stacked-Gate Etch (SAE), Self-Aligned Source etch (SAS), tunnel oxide, ONO films, and passivation scheme. Engineered 7 types of triple-well CMOS transistors used in the peripheral circuits. Successfully solved critical issues such as ESD, endurance and data retention. Demonstrated functional 8M flash die on 1st product lot. Studied manufacturing capability using DOE tools. Transferred the 0.35um technology to production Fab. Resolved process issues due to different equipment and modules. Further optimized the technology in the manufacturing environment. -
Mts Device Technology EngineerAmd Jun 1991 - Mar 19960.35um Flash EPROM technology development from start to its qualification, including device architecture, TCAD sims, testchip design, bench characterization, technology design rules, and technology qualification.0.5um EPROM Technology Development - Process variability, manufacturing yield enhancement, and product qualification.0.8um Virtual Ground EPROM Technology Development - Testchip design, Si integration flow, TCAD, and device characterization.0.8um EPROM Technology Development - Device characterization and resolution of ESD and charge gain/loss issues.
Harry Luan Skills
Harry Luan Education Details
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Purdue UniversityEe
Frequently Asked Questions about Harry Luan
What company does Harry Luan work for?
Harry Luan works for Nantero, Inc.
What is Harry Luan's role at the current company?
Harry Luan's current role is VP, CTO, Technologist, Semiconductor and Solid State Device Technology and Engineering.
What is Harry Luan's email address?
Harry Luan's email address is h.****@****ass.com
What is Harry Luan's direct phone number?
Harry Luan's direct phone number is +140898*****
What schools did Harry Luan attend?
Harry Luan attended Purdue University.
What skills is Harry Luan known for?
Harry Luan has skills like Ic, Analog, Cmos, Embedded Systems, Eda, Asic.
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