Harshdeep is a Lead Software Engineer at Cadence Design Systems, a leading provider of software, hardware, and services for electronic design. He has been working at Cadence since 2019, starting as a Software Engineer I and progressing to his current role in 2022.He is a verification expert with proficiency in functional verification using System Verilog and UVM, and vast experience in Ethernet protocol. He has contributed to the development of multiple verification IP products for Cadence, such as the 2.5G/5G/10G BaseT1 Ethernet, 10BaseT1s Ethernet, 100BaseT1 Ethernet, Flexible Ethernet, Base-R Ethernet, 100G per lane Ethernet, MacSec and IPsec. He has also supported customers in resolving technical issues and delivering high-quality solutions.Harshdeep has also independently authored and presented his paper titled "Verification Challenges & Solutions of 10BaseT1s Automotive Ethernet PHY" in DVCon Taiwan 2023.Harshdeep holds a Bachelor of Technology degree in Electronics Instrumentation and Control Engineering from YMCA University of Science & Technology, where he graduated in 2017. He is skilled in languages such as C, Verilog, System Verilog, and UVM. He has also hands-on experience in Linux operating system and tools such as Perforce. He is highly enthusiastic and dedicated to his work, and always eager to learn new technologies and skills.Apart from his full-time responsibilities as an engineer, Harshdeep enjoys travelling, trekking, playing basketball and cricket. He values teamwork, innovation, and customer satisfaction, and strives to achieve excellence in his field.