Harshit Makwana Email and Phone Number

Extensive experience in Verilog/SystemVerilog RTL coding, function/performance simulation debugging, and Lint/synthesis/CDC/FV/LEC checks. Proficient in developing Register Transfer Level (RTL) implementations that consistently meet competitive power, performance, and area targets. Skilled in synthesis, timing/power closure, and Field-Programmable Gate Array (FPGA)/silicon bring-up processes.Strong engineering professional with a Master of Technology -M Tech focused on Electronic Systems from the Indian Institute of Technology, Bombay.