Harshit Makwana

Harshit Makwana Email and Phone Number

Lead Design Engineer at Cadence | Ex. Samsung | IIT BOMBAY | Gold Medalist (๐Ÿ…) @ Cadence Design Systems
sweden
Harshit Makwana's Location
Bengaluru, Karnataka, India, India
About Harshit Makwana

Extensive experience in Verilog/SystemVerilog RTL coding, function/performance simulation debugging, and Lint/synthesis/CDC/FV/LEC checks. Proficient in developing Register Transfer Level (RTL) implementations that consistently meet competitive power, performance, and area targets. Skilled in synthesis, timing/power closure, and Field-Programmable Gate Array (FPGA)/silicon bring-up processes.Strong engineering professional with a Master of Technology -M Tech focused on Electronic Systems from the Indian Institute of Technology, Bombay.

Harshit Makwana's Current Company Details
Cadence Design Systems

Cadence Design Systems

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Lead Design Engineer at Cadence | Ex. Samsung | IIT BOMBAY | Gold Medalist (๐Ÿ…)
sweden
Website:
cadence.se
Employees:
10
Harshit Makwana Work Experience Details
  • Cadence Design Systems
    Lead Design Engineer
    Cadence Design Systems Oct 2023 - Present
    Bengaluru, Karnataka, India
  • Samsung Semiconductor
    Associate Staff Engineer
    Samsung Semiconductor Mar 2023 - Sep 2023
    Banglore
    NVMe IP Refactoring
  • Samsung Semiconductor
    Senior Engineer (Digital Ip/Circuit Chip Design)
    Samsung Semiconductor Aug 2020 - Apr 2023
    Banglore
  • Indian Institute Of Technology, Bombay
    M.Tech Thesis
    Indian Institute Of Technology, Bombay Jun 2019 - Aug 2020
    Mumbai, Maharashtra
    ๐——๐—ฒ๐˜€๐—ถ๐—ด๐—ป & ๐—ถ๐—บ๐—ฝ๐—น๐—ฒ๐—บ๐—ฒ๐—ป๐˜๐—ฎ๐˜๐—ถ๐—ผ๐—ป ๐—ผ๐—ณ ๐—ฑ๐—ถ๐—ด๐—ถ๐˜๐—ฎ๐—น-๐˜๐—ผ-๐˜๐—ถ๐—บ๐—ฒ ๐—ฐ๐—ผ๐—ป๐˜ƒ๐—ฒ๐—ฟ๐˜๐—ฒ๐—ฟ (๐——๐—ง๐—–) ๐—ณ๐—ผ๐—ฟ ๐˜€๐˜‚๐—ฏ๐˜€๐—ฎ๐—บ๐—ฝ๐—น๐—ถ๐—ป๐—ด ๐—ฏ๐—ฎ๐˜€๐—ฒ๐—ฑ ๐—ฎ๐—น๐—น ๐—ฑ๐—ถ๐—ด๐—ถ๐˜๐—ฎ๐—น ๐—ฃ๐—Ÿ๐—Ÿ.Literature survey of various subsampling PLL currently being used for reduction of jitter.Design of a highly linear DTC which can cover desired delay range with lower jitter for fractional-N subsampling PLL.

Harshit Makwana Education Details

Frequently Asked Questions about Harshit Makwana

What company does Harshit Makwana work for?

Harshit Makwana works for Cadence Design Systems

What is Harshit Makwana's role at the current company?

Harshit Makwana's current role is Lead Design Engineer at Cadence | Ex. Samsung | IIT BOMBAY | Gold Medalist (๐Ÿ…).

What schools did Harshit Makwana attend?

Harshit Makwana attended Indian Institute Of Technology, Bombay, L.d College Of Engineering - Ahmedabad, Government Polytechnic Ahmedabad 617.

Who are Harshit Makwana's colleagues?

Harshit Makwana's colleagues are Joรฃo Vicente Souto, Julia Katzman, Veenanjali Kyanam, Anubhav Srivastava, Shuling Chiang, Hadas Aizik, Lucas Gabriel Aeraf De Assis.

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