Harshit Patel

Harshit Patel Email and Phone Number

Silicon Design at AMD | Ex-Intel | MS @ USC @ AMD
santa clara, california, united states
Harshit Patel's Location
Portland, Oregon, United States, United States
Harshit Patel's Contact Details

Harshit Patel personal email

About Harshit Patel

Experienced Physical Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Application-Specific Integrated Circuits (ASIC), Analog Circuit Design, System on Chip (SoC) and Cores/Graphics Physical Design. Strong engineering professional with a Master's degree focused in Electrical and Computer Engineering from University of Southern California.

Harshit Patel's Current Company Details
AMD

Amd

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Silicon Design at AMD | Ex-Intel | MS @ USC
santa clara, california, united states
Website:
amd.com
Employees:
16705
Harshit Patel Work Experience Details
  • Amd
    Senior Member Of Technical Staff
    Amd Jan 2022 - Present
    Austin, Texas
    Technology Bring-up and PD Methodology development for MI Graphics/Zen Cores.
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  • Intel Corporation
    Soc Design Engineer
    Intel Corporation Aug 2020 - Dec 2021
    Hillsboro, Oregon, United States
    PPA studies on Graphics partitions using RTL2GDSII flow as part of DTCO for Intel's next generation process definition.
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  • Intel Corporation
    Senior Physical Design Engineer
    Intel Corporation Aug 2016 - Jul 2020
    Hillsboro, Oregon, United States
    Physical Design Lead of a Power Delivery Chip.RTL2GDSII: Synthesis, PnR, Floor-planning, UPF, Power grid, CTS, STA, FEV, RV (IR/EM), LV (DRV/Density) and ECO implementation. C4 Bump/MiM Cap planning. Worked with RTL/Analog/Val teams & SoC customers across different geographical locations for smooth execution achieving successful PRQ tape-out.
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  • Intel Corporation
    Physical Design Engineer
    Intel Corporation Aug 2013 - Jul 2016
    Hillsboro, Oregon, United States
    Physical Design and Integration (RTL2GDSII) of Multiple Power Delivery Hard IPs on 22nm, 14nm and 7nm SoCs.
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  • Intel Corporation
    Analog Engineer
    Intel Corporation Aug 2011 - Jul 2013
    Hillsboro, Oregon
    Analog Circuit Design Engineer for FIVR (Fully Integrated Voltage Regulator) IP for Intel's 4th generation Haswell (22nm) processors.
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Harshit Patel Skills

C C++ Verilog

Harshit Patel Education Details

Frequently Asked Questions about Harshit Patel

What company does Harshit Patel work for?

Harshit Patel works for Amd

What is Harshit Patel's role at the current company?

Harshit Patel's current role is Silicon Design at AMD | Ex-Intel | MS @ USC.

What is Harshit Patel's email address?

Harshit Patel's email address is ha****@****ail.com

What schools did Harshit Patel attend?

Harshit Patel attended University Of Southern California, Dwarkadas J. Sanghvi College Of Engineering, Wilson College Chowpatty, St. Xavier's High School.

What skills is Harshit Patel known for?

Harshit Patel has skills like C, C++, Verilog.

Who are Harshit Patel's colleagues?

Harshit Patel's colleagues are Tim Lu, Sthiti Deka, Anjan Sah, Shailish Ramautar, Xavier Lee, 罗春丽, Chase Cardwell.

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