Harsh Nakarani
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Harsh Nakarani Email & Phone Number

Graduate EE (VLSI) Student at San Jose State University | Actively looking for Internship and Full-time opportunities in Design Verification, RTL Design, FPGA. at Tessolve
Location: San Jose, California, United States 3 work roles 2 schools
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✓ Verified Jun 2026 3 data sources Profile completeness 86%

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Role
Graduate EE (VLSI) Student at San Jose State University | Actively looking for Internship and Full-time opportunities in Design Verification, RTL Design, FPGA.
Location
San Jose, California, United States
Company size

Who is Harsh Nakarani? Overview

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Quick answer

Harsh Nakarani is listed as Graduate EE (VLSI) Student at San Jose State University | Actively looking for Internship and Full-time opportunities in Design Verification, RTL Design, FPGA. at Tessolve, a company with 1250 employees, based in San Jose, California, United States. AeroLeads shows a matched LinkedIn profile for Harsh Nakarani.

Harsh Nakarani previously worked as Physical Design Intern at Tessolve and Teaching Assistant at San Jose State University. Harsh Nakarani holds Master Of Science - Ms, Electrical And Electronics Engineering, 3.48 from San Jose State University.

Company email context

Email format at Tessolve

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Tessolve

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Profile bio

About Harsh Nakarani

Master's graduate in Electrical Engineering from San Jose State University with 1.25 years of industry experience in RTL design. Actively seeking full-time opportunities in RTL Design, Design Verification, and FPGA development, with a passion for driving innovation in hardware design and verification.

Current workplace

Harsh Nakarani's current company

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Tessolve
Tessolve
Graduate EE (VLSI) Student at San Jose State University | Actively looking for Internship and Full-time opportunities in Design Verification, RTL Design, FPGA.
bangalore, karnataka, india
Website
Employees
1250
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3 roles

Harsh Nakarani work experience

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Physical Design Intern

Current

San Jose, California, United States

Jul 2024 - Present

Teaching Assistant

San Jose, California, United States

Grader and Instructional Assistant for students enrolled in Business Analytics Courses. Developing Python Script to automate data collection and data analysis.

Aug 2023 - May 2024

Hardware Engineer

Mumbai, Maharashtra, India

May 2021 - Jul 2022
Team & coworkers

Colleagues at Tessolve

Other employees you can reach at tessolve.com. View company contacts for 1250 employees →

2 education records

Harsh Nakarani education

Master Of Science - Ms, Electrical And Electronics Engineering, 3.48

Coursework: Digital System Design and Synthesis, Advanced Computer Architecture, Logic Verification using UVM, Digital Design for AI/DSP.

FAQ

Frequently asked questions about Harsh Nakarani

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What company does Harsh Nakarani work for?

Harsh Nakarani works for Tessolve.

What is Harsh Nakarani's role at Tessolve?

Harsh Nakarani is listed as Graduate EE (VLSI) Student at San Jose State University | Actively looking for Internship and Full-time opportunities in Design Verification, RTL Design, FPGA. at Tessolve.

Where is Harsh Nakarani based?

Harsh Nakarani is based in San Jose, California, United States while working with Tessolve.

What companies has Harsh Nakarani worked for?

Harsh Nakarani has worked for Tessolve, San Jose State University, and Infosys.

Who are Harsh Nakarani's colleagues at Tessolve?

Harsh Nakarani's colleagues at Tessolve include Sri Veerendra Pachhipala, Swetha Gajendran, Viveak R, Ritty Daniel, and Bhagavathi Somasundaram.

How can I contact Harsh Nakarani?

You can use AeroLeads to view verified contact signals for Harsh Nakarani at Tessolve, including work email, phone, and LinkedIn data when available.

What schools did Harsh Nakarani attend?

Harsh Nakarani holds Master Of Science - Ms, Electrical And Electronics Engineering, 3.48 from San Jose State University.

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