Responsible for block-level closure for a low-power design as well as top-level integration for SoC

Worked on various parts of the Digital Design process with different roles, while also helping automate tools, main projects are:-- Development of Continuous Gap Analysis system for benchmarking of FPGA implementation tools-- Hands on experience with Cadence Implementation Tools for implementation of Quasar Core-- Physical design, using OpenLANE of FPU Caravel using SKY130 library for Efabless Open-MPW Caravel shuttle program

A Train-to-recruit program which covered basics of the Digital Design flow using RISC-V architecture. Gained Hands-on Experience with Industrial Design and Verification standards, while working on the following projects:-- Development of AMBA APB supported low-speed IPs-- Integration of a simplified D-Cache in Swerv-EH1 Core, and it's verification-- Development of SystemVerilog based Layered Testbench for the Verification of Wishbone InterfaceGot Hands-on Experience with Commercial design and Verification tools-- Synopsys VCS, Verdi, Design Compiler(DC) and PrimeTime(PT)-- Mentor Modelsim and Questasim-- Intel Quartus Prime