Managing a team of 20+ analog designers and layout engineers developing custom analog/mixed signal IC's for mobile communications/computing. My team develops foundational IPs covering a wide breadth. IPs include high performance, high speed amplifiers, low power, low noise amplifiers, ADCs, DACs, power management circuits like buck/boost/inverting buck boost/SIDO converters, ldos, charge pumps etc. I'm in charge of setting tactical and strategic design execution goals which are in sync with product line business goals. My team and I are trusted by customers, management & peers for flawless and rapid execution. My management approach is hands on with a broad spectrum of direct technical contributions including detailed concept & feasibility studies, design lead, top & block level design, process & package development, customer liaison & project management. My goal is to build a world class IC development team and help every one of my team members consistently get better at what they do.In concurrence with my design director responsibilities, I was a chip owner and led a cross-functional team of 25+ engineers to develop industry's highest negative rail single inductor multiple output Boost Converter IC. My innovation, leadership, technical guidance helped solve challenging technical specifications. Silicon was released to market on time with several company first features.

Managed and led a team of 10+ analog designers developing functional safety certified (ASIL-C, ASIL-D) power management IC’s. My team developed critical roadmap IP's that includes high efficiency high current wide VIN (up to 48V) buck/boost/buck-boost converters. Control scheme implemented were voltage mode, peak/valley/average current mode, COT, AOT, DCS. I helped establish a new design site in Dallas by interviewing & hiring talented power management expert designers. My team successfully developed and did on time RTM of business unit's first ASIL-D safety rated PMIC. I managed the transition of challenging design execution from an international team to local development team.. I led team effort to resolve 200+ existing silicon bugs in less than 6 months and ramped to production on time. I also managed design transfer for 20+ market released devices from international development team to US based team.

As a design team leader, led team of analog and digital engineers to successfully execute product development cycle of multiple mixed signal IC’s with eventual ramp to production. I met with customers on a regular basis to discuss chip architecture, specifications and provide update on chip execution. Along with systems team I defined all analog & digital blocks required and also defined proper partitioning between analog and digital sections. I defined appropriate test strategy along with test engineering team, discussed & defined proper ESD strategy along with ESD experts. I established AMS verification scope. I also coordinated top-level and analog IP layout with layout engineers.Design team lead for the most highly integrated blood glucose meter device with MSP430 microcontroller, USB, LCD, 12-bit SAR ADC and AFE with 90 dB SNR performance. Drove architecture & design of complete AFE chain.Design team lead and analog designer for security authentication IC for automotive markets. Developed architecture for analog security shield.Designed various analog blocks such as low noise PGA, trans-impedance amplifier, LDO, ultra low ripple current mode charge pumps, voltage controlled oscillators, anti aliasing filters. Participated in design of 16 bit continuous time sigma delta modulator.

Led design development of inkjet security cartridge IC that qualify FRAM technology as an embedded non-volatile memory in company. First IC to implement active security mesh over the entire chip for intrusion detection within the organization. Defined intrusion detection mesh topology, scanning algorithm and designed mesh analog sensor. Designed an ultra-fast transient response LDO with 0 -50 mA current step load handling capability with only on-chip bypass capacitors. The LDO had a power failure detector with LDO back gate switching to preserve LDO bypass capacitor charge for graceful chip operation completion. Performed root cause analysis and debug of very poor initial FRAM yield and discovered a process defect.Led design development of successive generations of laser barcode scanner ASIC. Worked on design of analog blocks such as instrumentation amp, trans-impedance amp, gm-C filter, AGC loop, H-Bridge driver, Laser diode driver.

Mostly focused on high voltage motor driver design. Designed high voltage (20V - 42V) H-Bridge drivers with pre-drivers, high voltage high current charge pumps, dynamic current limiters & active shoot-through prevention circuits. Also designed several 400 - 600 MHz FLLs with 0.25% locking accuracy with triangular dithering capability.