Lead a team of engineers on Custom Analog & Mixed-Signal layout work, ensure a good quality layout is delivered on time. Frequently communicate with circuit designers to achieve optimum silicon performance

- A team leader for a 10-bit Successive Approximation (SAR) ADC project. Decide on design specifications, translate design specifications into blocks specification and monitor schematic design and layout activities. Lead Chip Level Floor planning, decide pad locations and orientation, calculate amount of power/ground pads required and decide on power network strategy. Verify chip level functionality and performance through simulations, decide on chip package selection, lead and review PCB design, lead and review test planning, and monitor bench test activities. The ADC achieved a 9.5 ENOB. The team consists of 4 Senior Engineers, 1 PhD student and 1 technician. - Involved in AI chip project. Lead Top Level floor plan, decide and confirm pad locations with packaging company. Design and verify power network, decide amount of power/ground pads and verify through circuit simulation. Assist on post layout verifications and tapeout submission. Lead PCB design for product prototyping.- Leading and Supervising 1 master student and 2 undergraduate students on a 14-bit SAR ADC project. - Designed and verified VCO for 128MHz clock generation. Waiting for packaging and testing.- Leading a motor controller design-kit project. Managing PCB design activity and firmware outsourcing.- Member of BLDC motor controller project. Lead and manage PCB design activity.- Responsible for layout quality check of PLL, ADC, transmitter and receiver blocks.- Responsible to set up post-APR merge and verification flow in Cadence domain for Chip level verification.- Did Analog and RF layout services.

- Designed and verified Comparator for 12-bit SAR ADC with offset of 400 uV.- Design and verified Comparator for 11-bit SAR ADC with offset of 700 uV.- Designed and tested POR with Brown-out detection.- Designed and tested Bandgap, Oscillator and Current bias.- Designed and tested capacitive sensor interface circuit based on phase detection technique. - Designed, layout and verified Comparator for Delta-Sigma ADC.- Worked on design specifications, schematic design and simulation, supervised layout implementation, post layout simulation of Analog blocks and post fabrication testing.

- Led a digital physical verification team. - Supervised a team to make sure all layout passed DRC and LVS before fabrication.- Involved in layout implementation of Analog blocks.- Designed and test capacitive sensor interface circuit based on phase detection technique.

A member of digital layout implementation team. Performed DRC, LVS and antenna for digital layout design.