Hassan Oukacha Email & Phone Number

London, Gb

Armonk, New York, Ny, Us

• Wrote test cases to uncover any bugs in the overall design, which include PCie Express • Integrated Pcie Express into the overall top level chip design in 5nm technology• Verified integrity of PCie Express high speed bus in 5 nm technology• Wrote testcases to verify the functionality and robustness of different blocks in 7 nm technology• Wrote AMS models for different IO analog circuits • Created testbenches to compare AMS models and schematics for each and every analog circuit• Wrote scripts to automate regression of comparing schematics and AMS models • Wrote post-simulation scripts to analyze regression results• Built UVM infrastructure and migrated all AMS testcases to the newly developed UVM environment

Eindhoven, Noord-Brabant, Nl

• Integrated both analog and digital IPs that form clock, reset, and power subsystem used across all 16 FinFETCompact (FFC) products• Performed top level simulations to insure the proper connection of all subsystem IPs• Built a set of AMS verification testcases to verify the functionality of subsystem (reset sequences, standbysequences, POR watchdog,...)• Designed Level shifter circuit and other sub-blocks used in General Purpose IOs and run all necessarysimulations to make sure that all IP requirements have been fulfilled• Supported SAR ADC design in 40 LPRF technology by providing architectural recommendations andsimulations to optimize the overall design and increase its robustness• Wrote different test cases to verify the integration of ADC and its functionality (static linearity, normalconversion, injected conversion, self-test,...)• Integrated different Python scripts to auto-generate test cases across different PVTs based on the test caseswritten for one specific corner. This ensures the reusability of test cases and save verification time and effort• Built Real Number SystemVerilog model for 16 FFC IOs

Eindhoven, Noord-Brabant, Nl

• Designed sub-blocks for SAR DAC in 16 FFC Technology• Created matrices and reports to track defects and errata associated with automotive products, which soon becamethe golden standards for executives and other business units in NXP• Implemented new FMEA system in Automotive Business Unit (BU)• Implemented best analog design practices and shared them with all designers in Automotive BU• Led Zero Defect initiative that introduced new quality standards, methodology, processes, and design workflows• Deployed new system to capture requirements, track them and test them and trained engineers to use it

Austin, Texas, Us

3rd Rotation: Design Quality• Led Freescale global process for 100% Root Cause Analysis of all relevant IP and SoC Defects to drive appropriate actions (Process, methodology enhancements and people trainings) to eliminate failures reoccurrence• Established new standards to identify potential failure modes and their associated causes, address, and document them for new IPs, changed IPs, and carryover IPs in new applications or environments.• Participated in Design reviews in order to collect the right data and shared the learning results with others• Enabled Requirements Engineering as an essential discipline in a product development lifecycle2nd Rotation: Corporate Quality• Led the effort to eliminate NTI (non-trouble identified) customer returns by applying Advanced Outlier Screening to tighten up the fabrication processes• Participated in designing Test Vehicle to simulate aging effects for 16nm FFC NPI• Led Design Product Data Management dPDM Ticketing System Initiative to improve this system and standardizeprocedures of filing and managing tickets across different business groups company-wide• Introduced JEDEC standards into Freescale dPDM system to achieve Freescale zero defect quality control andreduce tape-out revisions• Participated in Advanced Burn-in initiative for Auto MCU business group1st rotation: Microcontrollers Verification• Performed functional verification to key Microcontrollers products both in SOC and IP level• Wrote test cases to verify the functionality and integration of SRAM, Cache, SCG (clock controller), PCC(peripheral clock control), and other IPs• Insured a very high test coverage using C, Assembly, and SystemVerilog test cases• Analyzed behavior and waveforms of specific signals and worked with designers to solve problems that arose

Medford, Massachusetts, Us

Designed 60 GHZ circulator using CMOS IC design. This is the first time a circulator was designed using CMOS technology and run at such a high frequency. Post-processed the circulator chip in order to integrate the Nano-Ferrite material. tTested the functionality of the device in the 60GHZ frequency range using high frequency probes

Medford, Massachusetts, Us

AR Drone Navigation System Research Internship, Electrical Engineering Lab, Tufts University, Summer 2012 * Made AR Drone fly independently through a series of preset waypoints * Installed GPS chip, Wi-Fi chip and Arduino on the AR drone * Wrote Arduino program to analyze GPS coordinates and send commands accordingly to Drone via Wi-FiLensless Microscopy Research Internship, Nano Lab, Tufts University, Summer 2012 * Built microscope of 3μm resolution from a commercial camera without the use of lenses * Wrote MatLab program that reconstructs camera’s hologram to a clear and noiseless image * Implemented super pixel resolution program to further increase the image resolution to 2µm

Boston, Ma, Us

• Taught mathematics on a weekly basis to small groups of students• Applied and received fund from Massachusetts Department of Education to expand study group

Master Of Science (Ms), Electrical And Electronics Engineering

Bachelor'S Degree, Electrcal Engineering