Hung Chiew Khor Email & Phone Number

Penang, Malaysia

Penang, Malaysia

• Specialization in IP/Subsystem verification and validation:
• Technical lead for IP/Subsystem design verification.
• Scoping technical readiness, design verification strategy and plan.
• Developed TestPlan for pre-silicon, subsystem validation, hardware validation,
• Developed Testbench framework with UVM.
• Functional coverage and code coverage driven for IP quality in pre-silicon DV.

Penang, Malaysia

• Specialization in IP verification and validation:
• Developed testbench, test-framework using constrained random verification methodology VMM, System Verilog.
• Developed test cases for Altera Ethernet IPs verification and validation.
• Developed Test Plan.
• Functional and code coverage driven for IP quality.
• Hardware IP validation using Altera FPGA.

Penang, Malaysia

• Technical lead on Altera Quartus II Assembler for HSSI on altera 28nm devices (Arria V and Cyclone V):
• Coordinated Altera Quartus II HSSI POF support
• HSSI Device checkout
• Product Engineering support on HSSI feature
• FullChip Verification on HSSI especially PCS.
• Modelsim/VCS Simulation on HSSI.

Penang, Malaysia

• Specialization in develop, verification and validation: o HSSI model.o Altera Megafunction.o Altera Behavioral Model.
• Automated reporting system using Perl, PHP, Shell Scripting.
• Developed and automated HDL Coverage (using Modelsim) reporting system to measure the coverage for Altera Megafunctions and behavior models.
• Developed simulation model (in C++ language) for Altera megafunctions and behavior models.
• Developed Verilog based testbench for Altera Stratix IV/Arria II/Cyclone IV GX megafunction.