Vignesh Manoharan Email & Phone Number

Palo Alto, California, Us

Mountain View, California, Us

* Envisioned and created new random based Verification platform to exhaustively verify complex designs. This involved cross platform involvement and flow development.* Helped and designed unified SOC DV platform which can seamlessly be used for simulation, emulation, post-silicon and software bringup flow.* Created custom scripts and flows for auto generation of CPU C-tests which gets used across simulation and emulation platform. * Played pivotal role in building and strengthening the DV team in US and also the team in India.* And most importantly made sure to share the knowledge across the team members and hit all the required targets on time with quality.

Mountain View, California, Us

* Lead the efforts in building up the entire DV platform from ground up.* Built custom scripts for simulation flows, regressions, UVM RAL model generations etc.* Built multiple scalable custom UVM VIP's for proprietary designs.* Built multiple wrapper UVM VIP's around industry standard protocols to make it scalable and robust.* Built multiple block and cluster level UVM testbench using existing VIP's and flow setup.* Built configurable SOC DV platform using all the VIP's, block/cluster level UVM benches and taken care the entire simulation flow for both CPU based and non-CPU based flows.* Built, setup and enabled the GLS flows and path cleared the design using SDF's etc.* Helped in putting up the plans, setups, etc. for the Post-Silicon bringup. And also brought up the chip and tested them in the lab.* Also played key roles in building up the Verification team, helped all the team members to come up to speed and successfully deliver the 1st ASIC Chip at Aeva.

Santa Clara, California, Us

* Lead the efforts in setting up the entire Verification architecture and the development towards the same. Slashed the environment bring-up time by 99.8% using my Novel GUI based automation tool for UVM skeleton development. * Guided my entire team and helped them through the course of the project attaining the respective goals for the organizational growth and also towards their career growth.* Path cleared the enablement of multiple uncore interface like Universal Multi-resource Bus, Sideband interface, and other proprietary interlace. * Worked on SoC level validation of server chipset and lead the verification activities of the Utilitybox in Ice Lake Server project.* Involved in cross-functional SoC debug and also supported the emulation debug.* Wrote python scripts for faster debug of post processing logs and modified outputs of existing script with added features.* Worked on UVM, OVM, co-existing environments, RAL flows. Used Synopsys VCS tools and Verdi for extensive debugging.

Palo Alto, California, Us

* Worked on UVM, VIP flow development and lead my team towards zero functional bugs tapeout product. * Implement high level verification environments at both chip and block levels. * Verifying digital blocks and analog interface modules. * Worked in a System Verilog simulation & test bench environment using constraint randomization, coverage. * Worked on developing automation tools using python for building UVM testbench templates and test case flows. * Worked on implementing C-Model wrapper development flow for reference model verification using DPI Calls.* Worked in ARM based environment and SoC level verification flows.* Worked in simulation environment using Synopsys VCS and Cadence Incisive EDA Tools.

San Jose, Ca, Us

* Worked on UVM flow development, documentations and VIP development across the ATMEL sites globally. * Verifying digital blocks and analog interface modules. * Implement high level verification environments at both chip and module levels. * Write feature extraction, verification plans and contribute to chip test plan. * Worked in a System Verilog simulation & test bench environment using constraint randomization, coverage. * Worked with digital designers, analog designers, and verification engineers. * Write Verilog behavioral & bus functional models. Work on simulation environment using Synopsys VCS and Cadence Incisive EDA Tools. * Worked in ARM and micro-controller based environment. Implement and monitor Atmel QA standards.

San Diego, Ca, Us

* Worked on Block and SoC level verification of digital designs using Universal Verification Methodologies for Verifying Power Blocks. * Worked on Power Aware verification using Unified Power Format. * Conducted connectivity and memory checks as well as vector tests and analysis. * Worked on ARM based digital design and verification environment. Work on simulation environment using Synopsys VCS EDA Tool.* Worked on tests for sleep-wake-up process at functional level and validation process.

San Jose, Ca, Us

* Successfully taped out two Chips with Zero Functional bugs.* Worked on Block and SOC level verification of digital designs using OVM[Open Verification Methodology] and UVM[Universal Verification Methodology] for touch based SoC's.* Worked on ARM based digital design and verification test benches. * Worked on Power Aware Verification using UPF[Unified Power Format]. * Worked on Vector tests, memory checks and connectivity analysis. Work with cross-functional teams from design, verification and lab engineers. * Worked on simulation environment using Synopsys VCS and Mentor Graphics Questa EDA Tools.

Mumbai, Maharashtra, In

* Worked on developing feature extraction, progress and verification plans. * Worked on block level digital design and verification. * Creating VIP’s[Verification Intellectual Property] for serial protocols such as SPI, I2C using constraint randomization and coverage. * Supported AMBA AHB and SD-Card OVM VIP Development.* Work on simulation environment using Mentor Graphics QuestaSim EDA Tool.

* Developed verification and progress plans. * Created VIP’s[Verification Intellectual Property] and examples using VMM[Verification Methodology Manual], OVM[Open Verification Methodology] for Ethernet and SONET[Synchronous Optical Network] Protocols. * Work on SystemVerilog testbench environment. Test Case creation for tool testing using Synopsys VCS EDA tool.

* Developed examples in Verilog and SystemVerilog for labs. * VIP[Verification Intellectual Property] development using Open Vera and RVM[Reference Verification Methodology] for DES[Data Encryption Standard] and I2S Protocol. * Worked on SystemVerilog and VMM[Verification Methodology Manual] VIP’s for DES and AMBA AHB, LPC. * Handled SystemVerilog training labs. Tutorial development for testbench debug. Worked on simulation environment using Synopsys VCS and Mentor Graphics QuestaSim EDA Tools.

M.Tech, Vlsi Design

B.E, Electronics And Communication Engineering