Hemanth Kumar Balaji

Hemanth Kumar Balaji Email and Phone Number

Staff engineer (DI) - Samsung Austin @ Samsung Semiconductor
Hemanth Kumar Balaji's Location
Austin, Texas, United States, United States
Hemanth Kumar Balaji's Contact Details

Hemanth Kumar Balaji personal email

n/a

Hemanth Kumar Balaji phone numbers

About Hemanth Kumar Balaji

Physical Design Engineer with 10 years experience in Place and Route, Static Timing Analysis, Physical Verification and Power, IR, EManalysis, • Well versed with complete Netlist to GDS design flow, participated in all stages of the design.• Hands on experience with Floor planning, Placement, Clock Tree Synthesis, Routing, DFM.• Physical Verification (DRC, LVS, ERC, antenna rule check)• RC extraction and analysis.• Static Timing Analysis.• Analyzing timing and generating and implementing timing eco’s.• Experience in handling pre-silicon and post-silicon(Gate array) ECO flows (functional and timing).• Equivalence checking and analysis. • Constraint analysis and enhancement during initial RTL cycle.• Proficient in Scripting using PERL, Shell, TCL.CAD Tools - Design compiler for Synthesis, INNOVUS, ICC and Aprisa for Place and Route, Caliber for Physical Verification, Primetime for Static Timing Analysis and RedHawk for Power Analysis, Conformal for Equivalence Checking and Tweaker for ECO changelist.

Hemanth Kumar Balaji's Current Company Details
Samsung Semiconductor

Samsung Semiconductor

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Staff engineer (DI) - Samsung Austin
Hemanth Kumar Balaji Work Experience Details
  • Samsung Semiconductor
    Staff Engineer
    Samsung Semiconductor Apr 2022 - Present
  • Qualcomm
    Sr Engineer (Gpu Physical Design)
    Qualcomm Jul 2019 - Apr 2022
    San Diego, Ca, Us
  • Globalfoundries
    Physical Design Eng (Product Dev Engn)
    Globalfoundries Jan 2018 - Jul 2019
    Malta, Ny, Us
    o Involved in 14nm Tapeout handling signoff for two 1million+ instance size blocks and up to 1 GHz frequency.o Currently involved in 14nm SOC Project, working on two hierarchical (NOC) block of 750k+ instances and frequency 900 MHz and in analysis phase for 7nm project.o Attended Innovus Training for both block level and hierarchical design session at Cadence San Jose.o Working with junior member to bring up to speed for upcoming projects. o Tools used: Innvous, Tempus,
  • Arizona State University
    Graduate Teaching Assistant
    Arizona State University Dec 2016 - Jan 2018
    Tempe, Az, Us
    working as TA for EEE 334 -electrical circuits II
  • Arizona State University
    Graduate Teaching Assistant
    Arizona State University Aug 2016 - Dec 2016
    Tempe, Az, Us
    Worked as TA for EEE 352 Properties of electronic materials ..
  • Broadcom Inc.
    Physical Design Eng (Staff I Engineer - Ic Design)
    Broadcom Inc. Feb 2012 - Dec 2015
    Palo Alto, California, Us
    • Worked on several Projects from 28nm, 20nm and 16nm Technology nodes. The Designs were mostly modules in PHY ASICs. Block level stand cell complexity was from 100K to 4.4 million standard cell instances with multiple functional clocks and scan clocks.• Handled Physical Design on one challenging Design which had around 498 hard macros and 3.2 Million standard cell instances with multiple clock domains, Designed 12 different floor plan to come up with optimized placement of macros.• Handled designs which had divided clocks, timing optimization and CTS on paths from source and generated clock was challenging.• Defined Power analysis flow using VCD for toggling registers. Resolved IR drop by adding additional power straps, cell padding and script to specifically tie cells to nearest PG stap with least resistance. And Power EM violations were fixed increasing the metal/via widths.• Automated work flow by scripting in PERL and TCL.• Have experience in Place and route tools like ICC, Aprisa(atoptech), Innovus(basic use), ICC2(basic use) • Have experience in power analysis tools like redhawk, physical verification tool like calibre, • Have experience in STA tools like PT and ECO tools like tweaker.
  • Netlogic Microsystems
    Engineer - Ic Design
    Netlogic Microsystems Jan 2012 - Feb 2012
    Santa Clara, Ca, Us

Hemanth Kumar Balaji Skills

Ic Compiler Aprisa Calibre Physical Implementation Apache Physical Design Clock Tree Synthesis Tcl Perl Tweaker Icc 2 Innovus Static Timing Analysis Prime Time Lec Vlsi Integrated Circuit Design Verilog Asic Digital Electronics Logic Design Soc Eda Compilers Rtl Design Very Large Scale Integration C C++ Cadence Virtuoso Microsoft Office

Hemanth Kumar Balaji Education Details

  • Arizona State University
    Arizona State University
    Electronics And Communications Engineering
  • Anna University Chennai
    Anna University Chennai
    Electrical And Electronics Engineering

Frequently Asked Questions about Hemanth Kumar Balaji

What company does Hemanth Kumar Balaji work for?

Hemanth Kumar Balaji works for Samsung Semiconductor

What is Hemanth Kumar Balaji's role at the current company?

Hemanth Kumar Balaji's current role is Staff engineer (DI) - Samsung Austin.

What is Hemanth Kumar Balaji's email address?

Hemanth Kumar Balaji's email address is hb****@****omm.com

What is Hemanth Kumar Balaji's direct phone number?

Hemanth Kumar Balaji's direct phone number is +148093*****

What schools did Hemanth Kumar Balaji attend?

Hemanth Kumar Balaji attended Arizona State University, Anna University Chennai.

What skills is Hemanth Kumar Balaji known for?

Hemanth Kumar Balaji has skills like Ic Compiler, Aprisa, Calibre, Physical Implementation, Apache, Physical Design, Clock Tree Synthesis, Tcl, Perl, Tweaker, Icc 2, Innovus.

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