Henry Angulo Email & Phone Number

Us

Foothill Ranch, Ca, Us

Developing constrained-random coverage driven tests, test benches and test plans which are implemented with the UVM methodology with emphasis on design reuse. These are applied to the verification of proprietary SOC image processing ASIC's used in high speed-resolution motion picture camera's for the film industry world wide.

Dallas, Tx, Us

• Provided hands-on guidance to WIPRO engineers, with test plan development, writing tests, test bench architecture, coding with system Verilog VMM, setting up PERL script flow to run RTL simulations with ASIC/FPGA RTL, setting up PERL script flow to run Netlist post-route timing simulations, setting up TI DVTK flow to run regression tests with different seeds, generating pail-fail reports, and setting up/using the Synopsys PCI express/USB 2.0/3.0 VIPs to support power management/error injection scenarios.• Transitioned logic simulator from Synopsys VCS to cadence IUS, with minimal impact to WIPRO. • Ramped up WIPRO contractors, using system Verilog VMM methodology in development of constrained random test benches to verify new USB2.0/3.0 device/hub/host controller ASIC designs. Enabled management team to adjust contractor head count based on dynamic work load to keep labor costs to a minimum. • Transitioned logic simulator from Synopsys VCS to cadence IUS, with minimal impact to WIPRO during design verification of SATA-to-USB 2.0/3.0 device endpoint controller XHCI USB 2.0/3.0 host controller, achieving cost reduction in simulator/VIP's licensing cost.

Dallas, Tx, Us

• Developed SPECMAN test benches/test cases to support verification of PCI Express-based designs at chip/module levels, using a combination of constrained random and directed test cases. • Developed Verilog modular test bench architecture for verifying 1394 A/V controller ASICs designed around a common functional core that included an embedded ARM7 processor and DCTP cipher. • Created PERL scripts to support running RTL and Netlist timing simulations as well as regression tests with pass-fail report generation; mentored team members in using test benches to assist with writing test cases and simulation debugging. • Adapted Verilog modular test bench architecture to support verification of 1394 controller ASIC derivatives. Guided TI Japan/Dallas teams in using test bench to write test cases and debug RTL. • Learned and apply system Verilog VMM with AE support from Synopsys; developed a system Verilog packet generator wrapper and coverage models to support constrained random testing of AES functionality that was incorporated as a new feature in a cost reduced version of existing 1394 controller ASIC for set top box applications• Mentored two junior engineers to assist in development of chip/module-level test benches/test plans to support verification of PCI express switch. • Developed a SPECMAN-based test bench and test cases to support constrained random verification of a pci express to vbus multi-function bridge IP block.• Developed a SPECMAN-based test bench and test cases to support constrained random testing of a pci express to 1394b host controller ASIC. The test bench and ASIC reused parts of an existing design and test bench. Mentored junior engineer to assist in test bench and test writing effort.

Dallas, Tx, Us

• Worked on a multi-location team to support the design and verification of ASICs for 1394 applications, using the APPLE 1394 IP as design core. • Performed RTL-level design, using Verilog RTL, and logic synthesis, using Synopsys. Worked with other designers to perform functional verification and debugging of ASIC RTL. Performed gate-level post route timing simulations and post route static timing analysis, using Synopsys. Provided support to applications engineering with silicon evaluation and debugging. • Traveled to key customer sites to investigate silicon issues and to duplicate these in simulation to identify a software work around and logic fixes for implementation in next silicon release. • Worked with other team members to debug APPLE 1394 IP to adapt it for use in various 1394 chip designs; mentored other engineers in 1394 protocol/using the 1394 IP in chip design. • Supported SONY with design of 1394 video controller ASIC for use in their first-to-market 1394 hand-held camcorder. • Supported TI Germany team with static timing analysis/verification of CELYNX general purpose highly configurable 1394 video controller ASIC, which supported a DTCP cipher and transfer of video packets with multiple formats. • Worked with TI Japan engineers to develop 1394 video controller custom ASIC for SONY with embedded ARM7 to run 1394 transaction layer software on chip.

Dallas, Tx, Us

Successfully supported floor planning and static timing analysis of the PCIM ASIC, using a TI developed proprietary tool for pre-placement of design blocks prior to submitting Netlist to layout group right up to PG. This ASIC along with the other two ASICs were successfully deployed in USAF F16 mission computer upgrade program. Performed Netlist synthesis from VHDL RTL, using Synopsys. Performed post-route static timing analysis of Netlist by using Synopsys to generate timing reports. Learned PERL/created PERL scripts for processing timing reports to identify register-to-register setup-hold violations/find and fix violations in Netlist by the addition or subtraction of cell buffer delays in the register-to-register path; learned VHDL.

Dallas, Tx, Us

Provided support to internal/external customers processing designs through TI ASIC flow. Performed pre-layout IKOS QC simulations, using TDL, Netlist, and pre-route SDF timing files to verify accuracy. Submitted Netlist to layout group. Sent post-route SDF timing files to customers for at speed gate simulations. Ran post route IKOS QC simulations to verify accuracy of TDL and Netlist with post-route SDF prior to sending design database to FAB. Developed PERL scripting skills/learned TI ASIC flow operations. Learned importance of providing excellent design service to secure future design work from satisfied customers.

Dallas, Tx, Us

Supported design of digital beam steering controllers for steering an RF energy beam transmitted/received by phase array antenna. Developed digital hardware/software components of PC-based prototype phased array antenna design; directed lab technicians to perform building and testing of prototype design. Implemented production design on multi-layer printed circuit board, using MSI and LSI logic, PROMS, and programmable logic arrays. Implemented ASIC-based bit slice processor architecture in adaptive nulling phased array GPS antenna design to generate and steer attenuation of jammer signals received by antenna.

Supported design/maintenance of microprocessor electronics systems used for locating oil in land or ocean environments for controlling seismic energy generation. Installed firmware/hardware updates to existing vibrator control electronics to correct design problems/incorporate changes to improve seismic performance. Minimized downtime of prospecting crews to reduce impact to customer schedules/company revenue.

Dallas, Tx, Us

Breadboarded circuit designs and collected data on performance. Performed manufacturing tolerance stack up analysis of mechanical component designs, using dimensions obtained from engineering drawings. Wrote production test plans for circuit board assemblies. Collected temperature cycle data used by design engineers to evaluate performance of circuit designs and mechanical parts over military operating temperatures.

Bsee, Electrical Engineering

Engineering Core Courses